Datasheet

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LTC1264

1264fb

FEATURES

DESCRIPTIO

APPLICATIO S

TYPICAL APPLICATIO

High Speed, Quad Universal

Filter Building Block

■

High Speed, Up to 250kHz Center Frequency

■

Four Identical Filters in a 0.3" Wide Package

■

Clock-to-Center Frequency Ratio of 20:1

■

Double-Sampling, Improved Aliasing

■

Operates from ±2.37V to ±8V Power Supplies

■

Customized Version with Internal Resistors Available

■

Low Noise

■

Low Harmonic Distortion

■

Available in 24-Pin DIP and SO Wide Packages

The LTC

1264 consists of four identical, high speed 2nd

order switched-capacitor filter building blocks designed

for center frequencies up to 250kHz. Each building block,

together with three to five resistors, can provide 2nd order

functions like lowpass, highpass, bandpass and notch.

The center frequency of each 2nd order section is tuned via

an external clock. The clock-to-center frequency ratio is

internally set to 20:1, but it can be modified via external

resistors.

The aliasing performance of the LTC1264 is improved by

double-sampling each 2nd order section. Input signal

frequencies can reach up to twice the clock frequency

before any alias products will be detectable.

For Q ≤ 5 and for T

< 85°C, the maximum center

frequency is 160kHz. For Q ≤ 2, the maximum center

frequency is 250kHz. Up to 8th order filters can be realized

by cascading all four 2nd order sections.

A customized monolithic version of the LTC1264 includ-

ing internal thin film resistors can be obtained.

■

Digital Communications

■

Spread Spectrum Communications

■

Spectral Analysis

■

Loran Receivers

■

Instrumentation

50k

10k

50k

10k

1264 TA01

OUT

INV B

HPB/NB

BPB

LPB

AGND

LPA

BPA

HPA/NA

INV A

INV C

HPC/NC

BPC

LPC

–

CLK

LPD

BPD

HPD/ND

INV D

50k

10k

50k

10k

50k

LTC1264

MAXIMUM

CENTER

160kHz

120kHz

60kHz

POWER

SUPPLY

±7.5V

±5V

Single 5V

0.1µF

CLK

0.1µF

Clock-Tunable 8th Order Bandpass Filter, f

CENTER

= f

CLK

/20

FREQUENCY (Hz)

10k

GAIN (dB)

–10

–20

–30

–40

–50

–60

–70

–80

100k 1M

1264 TA02

Gain vs Frequency

100kHz Bandpass, f

–3dB

Bandwidth = f

CENTER

/10

, LTC and LT are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

Summary of content (16 pages)

PAGE 1
LTC1264 High Speed, Quad Universal Filter Building Block U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO High Speed, Up to 250kHz Center Frequency Four Identical Filters in a 0.3" Wide Package Clock-to-Center Frequency Ratio of 20:1 Double-Sampling, Improved Aliasing Operates from ±2.
PAGE 2
LTC1264 U RATI GS U W W W AXI U W (Note 1) U ABSOLUTE PACKAGE/ORDER I FOR ATIO TOP VIEW Total Supply Voltage (V + to V –) .............................. 16V Input Voltage (Note 2) ........... (V + + 0.3V) to (V – – 0.3V) Output Short-Circuit Duration .......................... Indefinite Power Dissipation ............................................. 400mW Burn-In Voltage ...................................................... 16V Operating Temperature Range ...............
PAGE 3
LTC1264 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Complete Filter) VS = ±5V, fCLK = 1MHz, all sides mode 1, fO = 50kHz, Q = 5, unless otherwise noted. PARAMETER DC Offset Voltage (Note 3) CONDITIONS VOS1 (DC Offset of Input Inverter) VOS2 (DC Offset of First Integrator) VOS3 (DC Offset of Second Integrator) VS = ±7.5V (fCLK is a Square Wave) VS = ±5V (fCLK is a Square Wave) VS = ±2.
PAGE 4
LTC1264 U W TYPICAL PERFOR A CE CHARACTERISTICS Typical Bandpass Gain Error vs Clock Frequency VS = ±5V 2 VS = ±7.5V 1 2.4 3.2 3.6 2.8 CLOCK FREQUENCY (MHz) 4 MODE 1 Q=4 TA = 25°C VS = ±5V 3 2 VS = ±7.5V 1 0 2.0 4.0 TYPICAL BNADPASS GAIN ERROR (dB) 3 0 2.0 5 5 MODE 1 Q=2 TA = 25°C TYPICAL BANDPASS GAIN ERROR (dB) TYPICAL BANDPASS GAIN ERROR (dB) 5 4 Typical Bandpass Gain Error vs Clock Frequency Typical Bandpass Gain Error vs Clock Frequency 2.4 3.2 3.6 2.
PAGE 5
LTC1264 U U U PI FU CTIO S V +, V – (Pins 7, 19): Power Supply Pins. The V + (Pin 7) and the V – (Pin 19) should each be bypassed with a 0.1µF capacitor to an adequate analog ground. The filter’s power supplies should be isolated from other digital or high voltage analog supplies. A low noise linear supply is recommended. Using a switching power supply will lower the signal-to-noise ratio of the filter. The supply during power-up should have a slew rate less than 1V/µs.
PAGE 6
LTC1264 U U U PI FU CTIO S CLK (Pin 18): Clock Input Pin. Any TTL or CMOS clock source with a square wave output and 50% duty cycle (±10%) is an adequate clock source for the device. The power supply for the clock source should not be the filter’s power supply. The analog ground for the filter should be connected to clock’s ground at a single point only. Table 1 shows the clock’s low and high level threshold values for a dual or single supply operation. Table 1.
PAGE 7
LTC1264 W U ODES OF OPERATIO optimum mode for high Q designs with fCLK to fCUTOFF (or fCENTER) ratios greater than 20:1. Please refer to the Maximum Frequency of Operation paragraph under Applications Information for a guide to the use of capacitor CC. CC R3 R2 N VIN R1 – S + Σ LP BP – ∫ + ∫ Please refer to the Maximum Frequency of Operation paragraph under Applications Information for a guide to the use of capacitor CC. Mode 2 is a combination of Mode 1 and Mode 3, shown in Figure 7.
PAGE 8
LTC1264 W U ODES OF OPERATIO CC R4 R3 R2 N VIN R1 – S + + Σ LP BP – ∫ ∫ Please refer to the Maximum Frequency of Operation paragraph under Applications Information for a guide to the use of capacitor CC. 1264 F07 1/4 LTC1264 AGND fi = fCLK ;f =f 20 O i √ 1 + R4 ; f = f R2 n O Mode 2n ( ) √ 1 + R2R4 1 – 1R3 ( 6.42•R4 ) R3 Q = 1.005 R2 HOHP = – R2 (AC GAIN, f > fn); HOHPn = – R2 R1 R1 HOBP = – R3 R1 ( 1– 1 R3 6.42•R4 ) tors RH and RL to create a notch.
PAGE 9
LTC1264 W U ODES OF OPERATIO CC √ R3 R2 HP VIN R1 √ f fi = CLK ; fn = fi 1 + RH 20 RL R2 fO = fi 1+ R4 R R HOLPn (f = 0)= G + G R2 RH RL R1 R4 – + + S Σ – LP BP ∫ RG ∫ RL ( R3R2) √ 1 + R2R4 Q = 1.005 – + 1/4 LTC1264 )( ) ( ( 1– 1 1 + R2 R4 ) 1 R3 6.42•R4 ) LOWPASS NOTCH OUTPUT RH AGND ( EXTERNAL OP AMP OR INPUT OP AMP OF THE LTC1264, SIDES A, B, C, D 1264 G09 Figure 9.
PAGE 10
LTC1264 U W U UO APPLICATI S I FOR ATIO Operating Limits The Typical Maximum Q vs Clock Frequency and Bandpass Gain Error graphs, under Typical Performance Characteristics, define an upper limit of operating Q for each LTC1264 2nd order section. These graphs indicate the power supply, fCLK and Q value conditions under which a filter implemented with an LTC1264 will remain stable when operated at temperatures of 85°C or less.
PAGE 11
LTC1264 U W U UO APPLICATI S I FOR ATIO For example, for an LTC1264 bandpass filter with fCENTER = 100kHz and fCLK = 2MHz, a 3.9MHz, 10mV input will produce a 100kHz, 10mV output. A 1st or 2nd order prefilter will reduce aliasing to acceptable levels in most cases. Table 4. Bandpass Design Specifications (fCENTER is center frequency of passband.) A GUIDE TO BANDPASS DESIGN Note: Reducing passband ripple or attenuation will decrease Q values. The filter order may also increase.
PAGE 12
LTC1264 W U U UO APPLICATI S I FOR ATIO R1 R1 INV B INV C R2 R2 HPB/NB HPC/NC R3 R3 STAGE 1 R5 R6 R6 R5 STAGE 3 R3 BPB BPC LPB LPC R5 SB LTC1264 SC V– AGND V+ CLK SA SD LPA LPD BPA BPD HPA/NA fCLK R6 R6 1.0 0.5 0 R5 –0.
PAGE 13
LTC1264 UO TYPICAL APPLICATI S Gain vs Frequency Linear Phase Clock-Tunable to 400kHz, Dual 4th Order Lowpass Filter R1 0 R1 OUT 1 IN 1 INV B –10 INV C R2 R2 HPB/NB HPC/NC R3 –20 R3 BPB BPC LPB LPC R4 GAIN (dB) R4 C C SB 0.1µF SC LTC1264 V– AGND V+ 8V C SD LPA LPD C –70 –80 10k R4 R3 100k FREQUENCY (Hz) BPD R3 R2 HPA/NA R2 INV A IN 2 INV D OUT 2 R1 C B 2 2 17.8k 20k 27.4k 27.4k 19.6k 21k 51.1k 75k 5pF 5pF A 2 17.8k 27.4k 19.6k 51.1k 5pF D 2 20k 27.
PAGE 14
LTC1264 UO TYPICAL APPLICATI S 100kHz, 8th Order Notch Filter, fCLK /fCENTER = 20:1 Gain vs Frequency R1 10 0 C R1 INV B INV C R2 R2 HPB/NB HPC/NC R3 0.1µF –20 R3 BPB BPC LPB LPC SB SC LTC1264 V+ CLK SA SD LPA LPD –30 –40 –50 V– AGND 7.5V –10 GAIN (dB) IN –7.5V R3 –60 0.1µF fCLK 2MHz VS = ±7.5V fCLK = 2MHz –70 –80 10k OUT R3 BPA 100k FREQUENCY (Hz) 1M 1264 TA06b BPD R2 R2 HPA/NA LTC1264 SIDE MODE R1 R2 R3 C HPD/ND INV A INV D C R1 R1 C B 1 1 36.5k 3.
PAGE 15
LTC1264 U PACKAGE DESCRIPTIO N Package 24-Lead PDIP (Narrow .300 Inch) (Reference LTC DWG # 05-08-1510) 1.280* (32.512) MAX 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 .255 ± .015* (6.477 ± 0.381) .300 – .325 (7.620 – 8.255) .130 ± .005 (3.302 ± 0.127) .045 – .065 (1.143 – 1.651) .020 (0.508) MIN .008 – .015 (0.203 – 0.381) ( +.035 .325 –.015 8.255 +0.889 –0.381 .065 (1.651) TYP N24 0405 .120 (3.048) MIN ) .018 ± .003 (0.457 ± 0.076) .100 (2.
PAGE 16
LTC1264 UO TYPICAL APPLICATI 8th Order Bandpass Filter, Linear Phase RH RL R1 VIN INV B LTC1264 SIDE MODE R1 R2 R3 R4 RH RL INV C R2 R2 HPB/NB HPC/NC R3 R3 BPB BPC R4 R4 LPB LPC C 0.1µF SB SC LTC1264 V– AGND 7.5V V+ CLK SA SD LPA LPD BPA BPD 1MHz –7.5V 0.1µF fCLK 1MHz 1.5MHz 2.0MHz R4 R4 C B 3 3a 97.6k 10.7k 12.4k 39.2k 39.2k 13.3k 10.7k 53.6 15.0k D 3 10.0k 29.4k 10.0k 27.4k 100.0k C 0pF 5pF 10pF R3 R3 A 3a 32.4k 10.7k 12.4k 11.