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LTC1272

1272fc

For more information www.linear.com/1272

TYPICAL APPLICATION

DESCRIPTION

12-Bit, 3µs, 250kHz

Sampling A/D Converter

The LTC1272 is a 3µs, 12-bit, successive approximation

sampling A/D converter. It has the same pinout as the

industry standard AD7572 and offers faster conversion

time, on-chip sample-and-hold, and single supply opera-

tion. It uses LTBiCMOS™ switched-capacitor technology

to combine a high speed 12-bit ADC with a fast, accurate

sample-and-hold and a precision reference.

The LTC1272 operates with a single 5V supply but can

also accept the 5V/–15V supplies required by the AD7572

(Pin23, the negative supply pin of the AD7572, is not con-

nected on the LTC1272). The LTC1272 has the same 0V to

5V input range as the AD7572 but, to achieve single supply

operation, it provides a 2.42V reference output instead of

the –5.25V of the AD7572. It plugs in for the AD7572 if the

reference capacitor polarity is reversed and a 1µs sample-

and-hold acquisition time is allowed between conversions.

The output data can be read as a 12-bit word or as two

8-bit bytes. This allows easy interface to both 8-bit and

higher processors. The LTC1272 can be used with a crystal

or an external clock and comes in speed grades of 3ms

and 8ms.

Single 5V Supply, 3µs, 12-Bit Sampling ADC

FEATURES

APPLICATIONS

AD7572 Pinout

12-Bit Resolution

3µs and 8µs Conversion Times

On-Chip Sample-and-Hold

Up to 250kHz Sample Rates

5V Single Supply Operation

No Negative Supply Required

On-Chip 25ppm/°C Reference

75mW (Typ) Power Consumption

ESD Protected on All Pins

24-Pin Narrow DIP and SOL Packages

High Speed Data Acquisition

Digital Signal Processing (DSP)

Multiplexed Data Acquisition Systems

Single Supply Systems

1024 Point FFT, f

= 250kHz, f

= 10kHz

10µF

REF

D11 (MSB)

D10

CLK IN

CLK OUT

HBEN

BUSY

LTC1272

DGND

D3/11

D2/10

D1/9

D0/8

AGND

µP

CONTROL

LINES

0.1µF

8 OR 12-BIT

PARALLEL

BUS

ANALOG INPUT

(0V TO 5V)

10µF

0.1µF

LTC1272 • F01

2.42V

OUTPUT

REF

FREQUENCY (kHz)

–140

AMPLITUDE (dB)

20 40 60 80

LTC1272 • F02

–120

–100

–80

–60

–40

–20

100 120

(N+D)

= 72.1

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

LTBiCMOS is a trademark of Linear Technology Corporation. All other trademarks are the

property of their respective owners.

Summary of content (22 pages)

PAGE 1
LTC1272 12-Bit, 3µs, 250kHz Sampling A/D Converter FEATURES n n n n n n n n n n n DESCRIPTION AD7572 Pinout 12-Bit Resolution 3µs and 8µs Conversion Times On-Chip Sample-and-Hold Up to 250kHz Sample Rates 5V Single Supply Operation No Negative Supply Required On-Chip 25ppm/°C Reference 75mW (Typ) Power Consumption ESD Protected on All Pins 24-Pin Narrow DIP and SOL Packages The LTC1272 is a 3µs, 12-bit, successive approximation sampling A/D converter.
PAGE 2
LTC1272 ABSOLUTE MAXIMUM RATINGS (Notes 1 and 2) Supply Voltage (VDD)...................................................6V Analog Input Voltage (Note 3)..................... –0.3V to 15V Digital Input Voltage.................................... –0.3V to 12V Digital Output Voltage......................–0.3V to VDD + 0.3V Power Dissipation................................................500mW Operating Temperature Range LTC1272-XAC, CC.....................................
PAGE 3
LTC1272 CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
PAGE 4
LTC1272 DYNAMIC ACCURACY (Note 4) fSAMPLE = 250kHz (LTC1272-3), 111kHz (LTC1272-8) LTC1272-XA/C SYMBOL PARAMETER CONDITIONS S/(N+D) Signal-to-Noise Plus Distortion Ratio 10kHz Input Signal MIN TYP 72 MAX UNITS dB THD Total Harmonic Distortion (Up to 5th Harmonic) 10kHz Input Signal –82 dB Peak Harmonic or Spurious Noise 10kHz Input Signal –82 dB ANALOG INPUT The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C
PAGE 5
LTC1272 ELECTRICAL CHARACTERISTICS Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to ground with DGND and AGND wired together, unless otherwise noted. Note 3: When the analog input voltage is taken below ground it will be clamped by an internal diode.
PAGE 6
LTC1272 PIN FUNCTIONS AIN (Pin 1): Analog Input, 0V to 5V Unipolar Input. VREF (Pin 2): 2.42V Reference Output. When plugging into an AD7572 socket, reverse the reference bypass capacitor polarity and short the 10Ω series resistor. AGND (Pin 3): Analog Ground. D11 to D4 (Pins 4-11): Three-State Data Outputs. DGND (Pin 12): Digital Ground. D3/11 to D0/8 (Pins 13-16): Three-State Data Outputs. CLK IN (Pin 17): Clock Input.
PAGE 7
LTC1272 TYPICAL PERFORMANCE CHARACTERISTICS Differential Nonlinearity 1.0 VDD = 5V fCLK = 4MHz INL ERROR (LSBs) 0.5 0 –0.5 –1.0 0 512 1024 1536 2048 2560 3072 3584 4096 CODE LTC1272 • G02 VDD Supply Current vs Temperature 8 VDD = 5V 15 10 5 7 CLOCK FREQUENCY (MHz) 20 400 300 200 6 5 4 100 –25 0 25 50 75 100 3 0 –55 125 –25 TEMPERATURE (°C) 0 25 75 50 LT1272 • G03 2.
PAGE 8
LTC1272 APPLICATIONS INFORMATION Conversion Details AIN During conversion, the internal 12-bit capacitive DAC output is sequenced by the SAR from the most significant bit (MSB) to the least significant bit (LSB). Referring to Figure 1, the AIN input connects to the sample-and-hold capacitor through a 300Ω/2.7k divider. The voltage divider allows the LTC1272 to convert 0V to 5V input signals while operating from a 4.5V supply. The conversion has two phases: the sample phase and the convert phase.
PAGE 9
LTC1272 APPLICATIONS INFORMATION Signal-to-Noise Ratio 1.0 0.5 ERROR (LSB) The Signal-to-Noise Ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency components at the A/D output. This includes distortion as well as noise products and for this reason it is sometimes referred to as Signal-to-Noise + Distortion [S/(N + D)]. The output is band limited to frequencies from DC to one half the sampling frequency.
PAGE 10
LTC1272 APPLICATIONS INFORMATION CS & RD t2 tCONV BUSY t13 ≥ 40ns* CLK IN t14 DB11 (MSB) DB10 DB1 DB0 (LSB) UNCERTAIN CONVERSION TIME FOR 30ns < t14 < 180ns *THE LTC1272 IS ALSO COMPATIBLE WITH THE AD7572 SYNCHRONIZATION MODES. LTC1272 • F05 Figure 5. RD and CLK IN for Synchronous Operation as in Figure 5. Nevertheless, even without observing this guideline, the LTC1272 is still compatible with AD7572 synchronization modes, with no increase in linearity error.
PAGE 11
LTC1272 APPLICATIONS INFORMATION CS & RD BUSY 50ns TYP CLK IN CLK OUT DB11 (MSB) DB10 DB1 DB0 (LSB) LTC1272 • F07 Figure 7. Operating Waveforms Using an External Clock Source for CLK IN LTC1272 11...110 + 11...101 TO DAC – 3 AGND 2 OUTPUT CODE CURVATURE CORRECTED BANDGAP REFERENCE FULL-SCALE TRANSITION 11...111 5V FS = 5V FS 1LSB = –––– 4096 00...011 VREF 00...010 00...001 0.1µF 00...
PAGE 12
LTC1272 APPLICATIONS INFORMATION 0V TO 5V ANALOG INPUT VIN + sential to low noise operation of the ADC and the foil width for these tracks should be as wide as possible. R3 15Ω A1 LT1007 1 AIN Noise: Input signal leads to AIN and signal return leads from AGND (pin 3) should be kept as short as possible to minimize input noise coupling. In applications where this is not possible, a shielded cable between source and ADC is recommended.
PAGE 13
LTC1272 APPLICATIONS INFORMATION There are two modes of operation as outlined by the timing diagrams of Figures 13 to 17. Slow Memory Mode is designed for microprocessors which can be driven into a Wait state, a Read operation brings CS and RD low which initiates a conversion and data is read when conversion is complete. The second is the ROM Mode which does not require microprocessor Wait states. A Read operation brings CS and RD low which initiates a conversion and reads the previous conversion result.
PAGE 14
LTC1272 APPLICATIONS INFORMATION CS t1 t5 t1 RD t10 t2 t11 tCONV BUSY t3 t6 OLD DATA DB11-DB0 DATA t7 NEW DATA DB11-DB0 t12 HOLD TRACK LTC1272 • F14 Figure 14. Slow Memory Mode, Parallel Read Timing Diagram Table 2.
PAGE 15
LTC1272 APPLICATIONS INFORMATION HBEN t8 t9 t8 t9 CS t1 t5 t1 t4 t5 RD t2 t10 tCONV t10 t11 BUSY t3 t6 t7 OLD DATA DB7-DB0 DATA t3 t7 NEW DATA DB7-DB0 NEW DATA DB11-DB8 t12 t12 HOLD TRACK LTC1272 • F15 Figure 15. Slow Memory Mode, Two Byte Read Timing Diagram Table 3.
PAGE 16
LTC1272 APPLICATIONS INFORMATION HBEN t8 t9 t8 t9 t8 t9 CS t1 t4 t5 t1 t4 t5 t1 t4 t5 RD t2 tCONV t11 t10 t2 BUSY t3 t7 t3 OLD DATA DB7-DB0 DATA t7 t3 NEW DATA DB11-DB8 NEW DATA DB7-DB0 t12 HOLD t7 t12 TRACK LTC1272 • F17 Figure 17. ROM Mode, Two Byte Read Timing Diagram Table 5.
PAGE 17
LTC1272 APPLICATIONS INFORMATION A23 A1 AS EN MC68000 ADDRESS DECODE RD R/W D0 LTC1272 CS BUSY DTACK D11 is accomplished with the single 16-bit Load instruction below: ADDRESS BUS DATA BUS D11 D0/8 HBEN ADDITIONAL PINS OMITTED FOR CLARITY LTC1272 • F18 Figure 18. LTC1272 MC68000 Interface For the 8085A For the Z80 LHLD (B000) LDHL, (B000) This is a two byte read instruction which loads the ADC data (address B000) into the HL register pair.
PAGE 18
LTC1272 APPLICATIONS INFORMATION Compatibility with the AD7572 time between conversions must be provided to allow the sample-and-hold to reacquire the analog input. Figure 22 shows that if the clock is synchronous with CS and RD, it is only necessary to short out the 10Ω series resistor and reverse the polarity of the 10µF bypass capacitor on the VREF pin. The –15V supply is not required and can be removed, or, because there is no internal connection to pin 23, it can remain unmodified.
PAGE 19
LTC1272 APPLICATIONS INFORMATION LTC1272 ANALOG INPUT (0V TO 5V) + 10µF 0.1µF 10Ω* A IN VDD VREF NC✝ D11 (MSB) CS D10 RD D9 µP DATA BUS –15V 0.1µF BUSY AGND HBEN D8 CLK OUT D7 CLK IN** D6 D0/8 D5 D1/9 D4 D2/10 DGND D3/11 + 2.42V* VREF OUTPUT µP CONTROL LINES 0.1µF + 5V 10µF 10µF † * THE LTC1272 HAS THE SAME 0V TO 5V INPUT RANGE BUT PROVIDES A 2.42V REFERENCE OUTPUT AS OPPOSED TO THE –5.25V OF THE AD7572.
PAGE 20
LTC1272 APPLICATIONS INFORMATION –15V LTC1272 10µF 0.1µF µP DATA BUS A IN VDD VREF NC✝ 0.1µF 5V 10µF 10µF † BUSY AGND D11 (MSB) CS D10 RD D9 HBEN D8 CLK OUT D7 CLK IN D6 D0/8 D5 D1/9 D4 D2/10 DGND D3/11 74HC04 S Q 1/2 D** 74HC74 CLK RD µP CONTROL LINES ➞ + 10Ω* + 2.42V* VREF OUTPUT ANALOG INPUT (0V TO 5V) + 0.1µF EXTERNAL ASYNCHRONOUS CLOCK OR * THE LTC1272 HAS THE SAME 0V TO 5V INPUT RANGE BUT PROVIDES A 2.42V REFERENCE OUTPUT AS OPPOSED TO THE –5.
PAGE 21
LTC1272 REVISION HISTORY (Revision history begins at Rev C) REV DATE DESCRIPTION PAGE NUMBER C 01/13 Edited text in the Dynamic Accuracy table heading to remove reference to the 166kHz (LTC1272-5) version. 3 1272fc Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representaForofmore information www.linear.
PAGE 22
LTC1272 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. N Package 24-Lead PDIP (Narrow .300 Inch) (Reference LTC DWG # 05-08-1510 Rev I) 1.280* (32.512) MAX 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 .255 ±.015* (6.477 ±0.381) .300 – .325 (7.620 – 8.255) .045 – .065 (1.143 – 1.651) .130 ±.005 (3.302 ±0.127) .020 (0.508) MIN .008 – .015 (0.203 – 0.381) ( +.035 .325 –.015 8.255 +0.