Datasheet

LTC1272
13
1272fc
For more information www.linear.com/1272
APPLICATIONS INFORMATION
There are two modes of operation as outlined by the tim-
ing diagrams of Figures 13 to 17. Slow Memory Mode is
designed for microprocessors which can be driven into a
Wait state, a Read operation brings CS and RD low which
initiates a conversion and data is read when conversion
is complete.
The second is the ROM Mode which does not require
microprocessor Wait states. A Read operation brings CS
and RD low which initiates a conversion and reads the
previous conversion result.
Figure 12. Internal Logic for Control Inputs CS, RD and HBEN
Figure 13. RD and CLK IN for Synchronous Operation
LTC1272 • F12
BUSY
FLIP
FLOP
CLEAR
QD
ACTIVE HIGH
ACTIVE HIGH
ENABLE THREE-STATE OUTPUTS
D11....D0/8 = DB11....DB0
ENABLE THREE-STATE OUTPUTS
D11....D8 = DB11....DB8
D7....D4 = LOW
D3/11....D0/8 = DB11....DB8
CONVERSION START
(RISING EDGE TRIGGER)
5V
HBEN
CS
RD
LTC1272
D11....D0/8 ARE THE ADC DATA OUTPUT PINS
DB11....DB0 ARE THE 12-BIT CONVERSION RESULTS
19
21
20
LTC1272 • F13
CS & RD
BUSY
CLK IN
≥ 40ns*
t
2
t
14
t
CONV
t
13
DB0
(LSB)
DB1DB10DB11
(MSB)
UNCERTAIN CONVERSION TIME FOR 30ns < t
14
< 180ns
THE LTC1272 IS ALSO COMPATIBLE WITH THE AD7572 SYNCHRONIZATION MODES.
SEE “DIGITAL INTERFACE” TEXT.
*
Table 1. Data Bus Output, CS and RD = Low
PIN 4 PIN 5 PIN 6 PIN 7 PIN 8 PIN 9 PIN 10 PIN 11 PIN 13 PIN 14 PIN 15 PIN 16
Data Outputs* D11 D10 D9 D8 D7 D6 D5 D4 D3/11 D2/10 D1/9 D0/8
HBEN = LOW DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
HBEN = HIGH DB11 DB10 DB9 DB8 LOW LOW LOW LOW DB11 DB10 DB9 DB8
Note: *D11 . . . D0/8 are the ADC data output pins
DB11 . . . DB0 are the 12-bit conversion results, DB11 is the MSB