Datasheet

ManualsBrandsLINEAR TECHNOLOGY ManualsData collecting ICsData acquisition IC - AD converter (ADC) Internal SOIC 24

LTC1273

LTC1275/LTC1276

127356fa

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Single Supply 5V or ±5V Operation

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300ksps Sample Rate

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75mW (Typ) Power Dissipation

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On-Chip 25ppm/°C Reference

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Internal Synchronized Clock; No Clock Required

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High Impedance Analog Input

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70dB S/(N + D) and 77dB THD at Nyquist

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±1/2LSB INL and ±3/4LSB DNL Max (A Grade)

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ESD Protected On All Pins

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24-Pin Narrow PDIP and SW Packages

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Variety of Input Ranges:

0V to 5V (LTC1273)

±2.5V (LTC1275)

±5V (LTC1276)

Effective Bits and Signal to (Noise + Distortion)

vs Input Frequency

REF

AGND

D11

D10

DGND

BUSY

HBEN

D0/8

D1/9

D2/10

D3/11

LTC1273

0.1µF

10µF

2.42V

REF

OUTPUT

ANALOG INPUT

(0V TO 5V)

10µF

0.1µF

8- OR 12-BIT

PARALLEL BUS

µP CONTROL

LINES

LTC1273/75/76 • TA01

INPUT FREQUENCY (Hz)

10k

EFFECTIVE BITS

100k 2M

LTC1273/75/76 • TA02

S/(N + D) (dB)

SAMPLE

= 300kHz

NYQUIST

FREQUENCY

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High Speed Data Acquisition

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Digital Signal Processing

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Multiplexed Data Acquisition Systems

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Audio and Telecom Processing

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Spectrum Analysis

The LTC

1273/LTC1275/LTC1276 are 300ksps, sam-

pling 12-bit A/D converters that draw only 75mW from

single 5V or ±5V supplies. These easy-to-use devices

come complete with 600ns sample-and-holds, precision

references and internally trimmed clocks. Unipolar and

bipolar conversion modes provide flexibility for various

applications. They are built with LTBiCMOS

switched

capacitor technology.

These devices have 25ppm/°C (max) internal references.

The LTC1273 converts 0V to 5V unipolar inputs from a

single 5V supply. The LTC1275/LTC1276 convert ±2.5V

and ±5V respectively from ±5V supplies. Maximum DC

specifications include ±1/2LSB INL, ±3/4LSB DNL and

25ppm/°C full scale drift over temperature. Outstanding

AC performance includes 70dB S/(N + D) and 77dB THD

at the Nyquist input frequency of 150kHz.

The internal clock is trimmed for 2.7µs maximum conver-

sion time. The clock automatically synchronizes to each

sample command eliminating problems with asynchro-

nous clock noise found in competitive devices. A high

speed parallel interface eases connections to FIFOs, DSPs

and microprocessors.

12-Bit, 300ksps Sampling

A/D Converters with Reference

Single 5V Supply, 300ksps, 12-Bit Sampling A/D Converter

FEATURES

DESCRIPTIO

APPLICATIO S

TYPICAL APPLICATIO

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

LTBiCMOS is a trademark of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

Summary of content (24 pages)

PAGE 1
LTC1273 LTC1275/LTC1276 12-Bit, 300ksps Sampling A/D Converters with Reference U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO Single Supply 5V or ±5V Operation 300ksps Sample Rate 75mW (Typ) Power Dissipation On-Chip 25ppm/°C Reference Internal Synchronized Clock; No Clock Required High Impedance Analog Input 70dB S/(N + D) and 77dB THD at Nyquist ±1/2LSB INL and ±3/4LSB DNL Max (A Grade) ESD Protected On All Pins 24-Pin Narrow PDIP and SW Packages Variety of Input Ranges: 0V to 5V (LTC1273) ±2.
PAGE 2
LTC1273 LTC1275/LTC1276 W W W AXI U U ABSOLUTE RATI GS (Notes 1 and 2) Supply Voltage (VDD) .............................................. 12V Negative Supply Voltage (VSS) LTC1275/LTC1276 .................................. – 6V to GND Total Supply Voltage (VDD to VSS) LTC1275/LTC1276 ............................................... 12V Analog Input Voltage (Note 3) LTC1273 .................................... – 0.3V to VDD + 0.3V LTC1275/LTC1276 .............. VSS – 0.3V to VDD + 0.
PAGE 3
LTC1273 LTC1275/LTC1276 U CO VERTER CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specfications are at TA = 25°C.
PAGE 4
LTC1273 LTC1275/LTC1276 U U DIGITAL I PUTS A D DIGITAL OUTPUTS The ● denotes the specifications which apply over the full operating temperature range, otherwise specfications are at TA = 25°C. (Note 5) LTC1273A/LTC1275A/LTC1276A LTC1273B/LTC1275B/LTC1276B MIN TYP MAX UNITS SYMBOL PARAMETER CONDITIONS VIH High Level Input Voltage VDD = 5.25V ● VIL Low Level Input Voltage VDD = 4.
PAGE 5
LTC1273 LTC1275/LTC1276 WU TI I G CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specfications are at TA = 25°C.
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LTC1273 LTC1275/LTC1276 WU TI I G CHARACTERISTICS (Note 5) ROM Mode, Parallel Read Timing Diagram Slow Memory Mode, Parallel Read Timing Diagram CS CS t1 t5 t1 t1 t1 t5 t4 t4 t5 RD RD t2 t11 tCONV t10 t11 t2 tCONV t2 tCONV BUSY BUSY t7 t6 t3 OLD DATA DB11 TO DB0 DATA t12 HOLD OLD DATA DB11 TO DB0 DATA TRACK LTC1273/75/76 • TA03 NEW DATA DB11 TO DB0 t12 HOLD t7 t3 t7 t3 NEW DATA DB11 TO DB0 t12 TRACK LTC1273/75/76 • TA04 Slow Memory Mode, Two Byte Read Timing Diagr
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LTC1273 LTC1275/LTC1276 U W TYPICAL PERFOR A CE CHARACTERISTICS Integral Nonlinearity Differential Nonlinearity 1.0 1.0 0.5 0.5 Supply Current vs Temperature 25 0 –0.5 SUPPLY CURRENT (mA) DNL ERROR (LSB) INL ERROR (LSB) 20 0 –0.5 15 10 5 –1.
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LTC1273 LTC1275/LTC1276 U W TYPICAL PERFOR A CE CHARACTERISTICS Acquisition Time vs Source Impedance Intermodulation Distortion Plot fSAMPLE = 300kHz fIN1 = 29.37kHz fIN2 = 32.
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LTC1273 LTC1275/LTC1276 UO U U PI FU CTI S VSS (Pin 23): Negative Supply. – 5V for LTC1275/ LTC1276. Bypass to AGND with 0.1µF ceramic. VDD (Pin 24): Positive Supply, 5V. Bypass to AGND (10µF tantalum in parallel with 0.1µF ceramic). NC (Pin 23): No Connection for LTC1273. Table 1.
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LTC1273 LTC1275/LTC1276 U W U UO APPLICATI S I FOR ATIO CONVERSION DETAILS The LTC1273/LTC1275/LTC1276 use a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 12-bit parallel or 2-byte output. The ADCs are complete with a precision reference and an internal clock. The control logic provides easy interface to microprocessors and DSPs. (Please refer to the Digital Interface section for the data format.
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LTC1273 LTC1275/LTC1276 W U U UO S I FOR ATIO Effective Number of Bits The Effective Number of Bits (ENOBs) is a measurement of the resolution of an ADC and is directly related to the S/(N + D) by the equation: N = [S/(N + D) – 1.76]/6.02 12 74 11 68 10 62 9 56 8 50 7 6 5 fSAMPLE = 300kHz –10 THD 2nd HARMONIC 3rd HARMONIC –20 –30 –40 –50 –60 –70 –80 –90 1k 4 10k 100k 1M INPUT FREQUENCY (Hz) 10M LTC1273/75/76 • F04 Figure 4.
PAGE 12
LTC1273 LTC1275/LTC1276 U W U UO APPLICATI S I FOR ATIO Figure 5 shows the IMD performance at a 30kHz input. 0 fSAMPLE = 300kHz fIN1 = 29.37kHz fIN2 = 32.446kHz AMPLITUDE (dB) –20 –40 –60 –80 –100 –120 0 20 40 60 80 100 120 140 160 FREQUENCY (kHz) LTC1273/75/76 • F05 Figure 5. Intermodulation Distortion Plot Peak Harmonic or Spurious Noise The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC.
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LTC1273 LTC1275/LTC1276 W U U UO APPLICATI S I FOR ATIO reference pin. The VREF pin must be driven to at least 2.45V to prevent conflict with the internal reference. The reference should be driven to no more than 4.8V to keep the input span within the ±5V supplies. In the LTC1273/ LT1276, the input spans are 0V to 5V and ±5V respectively with the internal reference.
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LTC1273 LTC1275/LTC1276 UO 10k U R1 10k W ANALOG INPUT 0V TO 5V U APPLICATI S I FOR ATIO + R2 10k AIN – 5V R9 20Ω R4 100k R5 4.3k FULL SCALE 5V ADJUST R3 100k R7 100k R6 400Ω LTC1273 R8 LTC1273/75/76 • F10b 10k OFFSET ADJUST ANALOG INPUT ±2.5V (LTC1275) ±5V (LTC1276) R1 10k + R2 10k AIN – R4 100k R5 4.3k FULL SCALE 5V ADJUST R3 100k R7 100k R6 200Ω LTC1275 LTC1276 R8 LTC1273/75/76 • F10c 20k OFFSET ADJUST –5V Figure 10b.
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LTC1273 LTC1275/LTC1276 W U U UO APPLICATI S I FOR ATIO 1 ANALOG INPUT CIRCUITRY + – DIGITAL SYSTEM LTC1273 AIN AGND VREF 3 2 10µF DGND VDD 24 0.1µF 10µF 12 0.1µF GROUND CONNECTION TO DIGITAL CIRCUITRY ANALOG GROUND PLANE LTC1273/75/76 • F11 Figure 11. Power Supply Grounding Practice error voltage in series with the input signal, attention should be paid to reducing the ground circuit impedances as much as possible.
PAGE 16
LTC1273 LTC1275/LTC1276 W U U UO APPLICATI S I FOR ATIO 8MSBs) where it can be read in two read cycles. The 4MSBs always appear on D11...D8 whenever the threestate output drivers are turned on. on all three inputs to initiate a conversion. Once initiated it cannot be restarted until the conversion is complete. Converter status is indicated by the BUSY output, and this is low while conversion is in progress.
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LTC1273 LTC1275/LTC1276 W U U UO APPLICATI S I FOR ATIO HBEN t8 t9 t8 t9 CS t1 t5 t1 t4 t5 RD t10 t2 t10 t11 t CONV BUSY t3 t6 OLD DATA DB7-DB0 DATA t7 t3 t7 NEW DATA DB11-DB8 NEW DATA DB7-DB0 t12 HOLD t12 TRACK LTC1273/75/76 • F14 Figure 14. Slow Memory Mode, Two Byte Read Timing Diagram Table 3.
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LTC1273 LTC1275/LTC1276 W U U UO APPLICATI S I FOR ATIO CS t1 t5 t4 t1 t5 t4 RD t11 t2 t CONV t2 t CONV BUSY t3 t7 DATA t3 t7 OLD DATA DB11-DB0 NEW DATA DB11-DB0 t12 t12 HOLD TRACK LTC1273/75/76 • F15 Figure 15. ROM Mode, Parallel Read Timing Diagram (HBEN = LOW) Table 4.
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LTC1273 LTC1275/LTC1276 W U U UO APPLICATI S I FOR ATIO TMS320C25 Figure 17 shows an interface between the LTC1273 and the TMS320C25. The W/R signal of the DSP initiates a conversion and conversion results are read from the LTC1273 using the following instruction: IN D, PA A23 A1 ADDRESS BUS AS EN LTC1273/75/76 MC68000 CS BUSY DTACK RD R/W D11 D11 DATA BUS D0 where D is Data Memory Address and PA is the PORT ADDRESS.
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LTC1273 LTC1275/LTC1276 W U U UO APPLICATI S I FOR ATIO This is a two byte read instruction which loads the ADC data (address B000) into the HL register pair. During the first read operation, BUSY forces the microprocessor to WAIT for the LTC1273 conversion. No WAIT states are inserted during the second read operation when the microprocessor is reading the high data byte. TMS32010 Microcomputer current so it can be accurately driven by the unbuffered MUX.
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LTC1273 LTC1275/LTC1276 W U U UO APPLICATI S I FOR ATIO Demodulating a Signal by Undersampling with LTC1275 Figure 23 shows a 455kHz amplitude modulated input undersampled by the LTC1275. With a 227.5kHz sample rate, the converter provides a 100dB noise floor and 68dB distortion when digitizing the 455kHz AM input. A time domain view of the demodulation is shown in Figure 25. The top trace shows the 455kHz waveform modulated by a – 6dB, 5kHz signal.
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LTC1273 LTC1275/LTC1276 U W U UO APPLICATI S I FOR ATIO 7V 65Ω 5V 2N2369 65Ω 10µF 2N2369 400k 10µF 1N457 2N5771 REFOUT 20k 620Ω LM134 AIN 250pF POLYSTYRENE 45.3Ω VDD LTC1273 12-BIT DATA OUTPUT CS VSS GND RD BUSY 74HC03 1N457 45.3Ω 74HC74 5V D START↑ Q CLK Q CLR 1k 1N4148 10k 5V D 5V STOP↑ DATA LATCH SIGNAL Q CLK 1N4148 100pF Q CLR 1k 100k 0.001µF 1k 5V 10k 10pF LTC1273/75/76 • F26 Figure 26.
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LTC1273 LTC1275/LTC1276 U PACKAGE DESCRIPTIO N Package 24-Lead PDIP (Narrow .300 Inch) (Reference LTC DWG # 05-08-1510) 1.280* (32.512) MAX 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 .255 ± .015* (6.477 ± 0.381) .300 – .325 (7.620 – 8.255) .130 ± .005 (3.302 ± 0.127) .045 – .065 (1.143 – 1.651) .020 (0.508) MIN .008 – .015 (0.203 – 0.381) ( +.035 .325 –.015 +0.889 8.255 –0.381 .065 (1.651) TYP N24 0405 .120 (3.048) MIN ) .018 ± .003 (0.457 ± 0.076) .
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LTC1273 LTC1275/LTC1276 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1272-3 12-Bit, 250ksps ADC 5V Single Supply, Internal Reference, AD7572 Pinout LTC1278-4 12-Bit, 400ksps, Single Channel ADC 5V or ±5V Supplies, 0V to 5V or ±2.5V Input Range LTC1278-5 12-Bit, 500ksps, Single Channel ADC 5V or ±5V Supplies, 0V to 5V or ±2.5V Input Range LTC1403/LTC1403-1 12-Bit, 2.