Datasheet

ManualsBrandsLINEAR TECHNOLOGY ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal SOIC 24

LTC1274/LTC1277

12-Bit, 10mW, 100ksps

ADCs with 1µA Shutdown

ITY

ESCRIPTIO

The LTC

1274/LTC1277 are 8µs sampling 12-bit A/D

converters which draw only 2mA (typ) from single 5V or

±5V supplies. These easy-to-use devices come complete

with a 2µs sample-and-hold, a precision reference and an

internally trimmed clock. Unipolar and bipolar conversion

modes add to the flexibility of the ADCs.

Two power-down modes are available in the LTC1277. In

Nap mode, the LTC1277 draws only 180µA and the instant

wake-up from Nap mode allows the LTC1277 to be pow-

ered down even during brief inactive periods. In Sleep

mode only 1µA will be drawn. A REFRDY signal is used to

show the ADC is ready to sample after waking up from

Sleep mode. The LTC1274 also provides the Sleep mode

and REFRDY signal.

The A/D converters convert 0V to 4.096V unipolar inputs

from a single 5V supply or ±2.048V bipolar inputs from

±5V supplies.

The LTC1274 has a single-ended input and a 12-bit

parallel data format. The LTC1277 offers a differential

input and a 2-byte read format. The bipolar mode is

formatted as 2’s complement for the LTC1274 and offset

binary for the LTC1277.

■

Low Power Dissipation: 10mW

■

Sample Rate: 100ksps

■

Samples Inputs Beyond Nyquist, 72dB S/(N + D)

and 82dB THD at f

= 100kHz

■

Single Supply 5V or ±5V Operation

■

Power Shutdown to 1µA in Sleep Mode

■

180µA Nap Mode (LTC1277) with Instant Wake-Up

■

Internal Reference Can Be Overdriven

■

Internal Synchronized Clock

■

0V to 4.096V or ±2.048V Input Ranges (1mV/LSB)

■

24-Lead SO Package

, LTC and LT are registered trademarks of Linear Technology Corporation.

Supply Current vs Sample Rate with

Sleep and Nap Modes

SAMPLE RATE (Hz)

SUPPLY CURRENT (µA)

10000

1000

100

0.1 1k 100k

LTC1274/77 • TA02

101 10k100

WITHOUT SLEEP OR NAP

NAP = 5V

(SLEEP MODE)

NAP = REFRDY

(SLEEP MODE)

NAP MODE

REF

= 4.7µF

■

Battery-Powered Portable Systems

■

High Speed Data Acquisition for PCs

■

Digital Signal Processing

■

Multiplexed Data Acquisition Systems

■

Audio and Telecom Processing

■

Spectrum Analysis

–

REF

AGND

REFRDY

SLEEP

NAP

DGND

BUSY

CONVST

HBEN

LOGIC

D0/8

D1/9

D2/10

D3/11

LTC1277

0.1µF

10µF

ANALOG

DIFFERENTIAL INPUTS

(0V TO 4.096V)

2.42V

REF

OUTPUT

10µF

0.1µF

8-BIT

PARALLEL

BUS

µP

CONTROL

LINES

OPTIONAL 3V SUPPLY

TO INTERFACE WITH 3V

PROCESSOR

LTC1274/77 • TA01

Single 5V Supply, 10mW, 100kHz, 12-Bit ADC

Summary of content (20 pages)

PAGE 1
LTC1274/LTC1277 12-Bit, 10mW, 100ksps ADCs with 1µA Shutdown U FEATURES DESCRIPTIO ■ The LTC ®1274/LTC1277 are 8µs sampling 12-bit A/D converters which draw only 2mA (typ) from single 5V or ±5V supplies. These easy-to-use devices come complete with a 2µs sample-and-hold, a precision reference and an internally trimmed clock. Unipolar and bipolar conversion modes add to the flexibility of the ADCs.
PAGE 2
LTC1274/LTC1277 W W W AXI U U ABSOLUTE RATI GS (Notes 1, 2) Supply Voltage (VDD) ................................................ 7V Negative Supply Voltage (VSS) Bipolar Operation Only .......................... – 6V to GND Total Supply Voltage (VDD to VSS) Bipolar Operation Only ....................................... 12V Analog Input Voltage (Note 3) Unipolar Operation ................... – 0.3V to VDD + 0.3V Bipolar Operation............... VSS – 0.3V to VDD + 0.
PAGE 3
LTC1274/LTC1277 U U A ALOG I PUT (Note 5) SYMBOL PARAMETER CONDITIONS VIN Analog Input Range (Note 10) 4.75V ≤ VDD ≤ 5.25V (Unipolar) 4.75V ≤ VDD ≤ 5.25V, – 5.25V ≤ VSS ≤ – 2.45V (Bipolar) ● ● IIN Analog Input Leakage Current CS = High ● CIN Analog Input Capacitance Between Conversions (Sample Mode) During Conversions (Hold Mode) W U DY A IC ACCURACY MIN TYP MAX 0 to 4.096 ±2.
PAGE 4
LTC1274/LTC1277 U U DIGITAL I PUTS A D DIGITAL OUTPUTS (Note 5) SYMBOL PARAMETER CONDITIONS IOZ High-Z Output Leakage D11 to D0/8 VOUT = 0V to VDD, CS High ● COZ High-Z Output Capacitance D11 to D0/8 CS High (Note 10) ● ISOURCE Output Source Current VOUT = 0V – 10 mA ISINK Output Sink Current VOUT = VDD 10 mA W U POWER REQUIRE E TS MIN TYP MAX UNITS ±10 µA 15 pF (Note 5) SYMBOL PARAMETER CONDITIONS MIN VDD Positive Supply Voltage (Notes 11, 12) Unipolar and Bipolar Mode
PAGE 5
LTC1274/LTC1277 WU TI I G CHARACTERISTICS (Note 5) See Figures 13 to 17. SYMBOL PARAMETER CONDITIONS t16 HBEN↓ to Low Byte Data Valid CL = 100pF (LTC1277 Only) ● t17 HBEN↑ to RD↓ Setup Time (Note 10) (LTC1277 Only) ● 10 ns t18 RD↑ to HBEN↓ Setup Time (Note 10) (LTC1277 Only) ● 10 ns The ● denotes specifications which apply over the full operating temperature range; all other limits and typicals TA = 25°C.
PAGE 6
LTC1274/LTC1277 U W TYPICAL PERFORMANCE CHARACTERISTICS S/(N + D) vs Input Frequency and Amplitude Signal-to-Noise Ratio (Without Harmonics) vs Input Frequency 80 70 VIN = – 20dB 50 40 30 20 VIN = – 60dB 10 50 40 30 100k INPUT FREQUENCY (Hz) 1M –60 2ND HARMONIC –80 THD 3RD HARMONIC –100 fSAMPLE = 100kHz 0 10k 2M –40 20 10 fSAMPLE = 100kHz 0 10k –20 60 DISTORTION (dB) SIGNAL-TO-NOISE RATIO (dB) SIGNAL/(NOISE + DISTORTION)(dB) 60 0 fSAMPLE = 100kHz VIN = 0dB 70 100k INPUT FREQUENC
PAGE 7
LTC1274/LTC1277 U W 3.0 fSAMPLE = 100kHz 2.0 1.5 1.0 0.5 0 –55 –25 50 25 75 0 TEMPERATURE (°C) 100 125 0 2.435 fSAMPLE = 100kHz –10 2.430 –20 –30 –40 DGND (VRIPPLE = 0.1V) –50 –60 V (V SS RIPPLE = 10mV) –70 –80 –100 10 100 RIPPLE FREQUENCY (kHz) 1 2.415 1000 2.405 Supply Current vs Supply Voltage 8 1000 SUPPLY CURRENT (µA) 1 TA = 25°C 9 WITHOUT SLEEP OR NAP 2.5 1.0 0 10 CREF = 4.7µF 1.
PAGE 8
LTC1274/LTC1277 U U U PI FU CTIO S RD (Pin 20): Read Input. This enables the output drivers when CS is low. D7 to D4* (Pins 8 to 11): Three-State Data Outputs. CS (Pin 21): The Chip Select input must be low for the ADC to recognize CONVST and RD inputs. D3/11 to D0/8* (Pins 13 to 16): Three-State Data Outputs. D11 is the Most Significant Bit. BUSY (Pin 21): The BUSY output shows the converter status. It is low when a conversion is in progress.
PAGE 9
LTC1274/LTC1277 W BLOCK DIAGRA S LTC1274 CSAMPLE VDD AIN ZEROING SWITCHES VREF VSS (0V FOR UNIPOLAR MODE OR –5V FOR BIPOLAR MODE) 2.42V REF REFRDY COMPARATOR 12-BIT CAPACITIVE DAC AGND DGND 12 SUCCESSIVE APPROXIMATION REGISTER INTERNAL CLOCK D11 • • • OUTPUT LATCHES D0 CONTROL LOGIC LTC1274 • BD SLEEP CONVST RD CS BUSY LTC1277 CSAMPLE AIN+ VDD AIN– VREF ZEROING SWITCHES VSS (0V FOR UNIPOLAR MODE OR –5V FOR BIPOLAR MODE) 2.
PAGE 10
LTC1274/LTC1277 WU W TI I G DIAGRA S CS to CONVST Setup Timing CS to RD Setup Timing CS CS t1 t2 RD CONVST LTC1274/77 • TD01 LTC1274/77 • TD02 SLEEP to REFRDY Wake-Up Timing NAP to CONVST Wake-Up Timing (LTC1277) NAP SLEEP t3 t14 CONVST REFRDY LTC1274/77 • TD03 LTC1274/77 • TD04 U W U U APPLICATIONS INFORMATION CONVERSION DETAILS The LTC1274/LTC1277 use a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 12-bit parallel output.
PAGE 11
LTC1274/LTC1277 U W U U APPLICATIONS INFORMATION using an FFT algorithm, the ADCs’ spectral content can be examined for frequencies outside the fundamental. Figures 2a and 2b show typical LTC1274 FFT plots. 0 AMPLITUDE (dB) 68 NYQUIST FREQUENCY 10 9 62 56 8 50 7 6 5 4 3 2 1 fSAMPLE = 100kHz 0 10k 100k INPUT FREQUENCY (Hz) 1M 2M LTC1274/77 • F03 Figure 3. ENOBs and S/(N + D) vs Input Frequency fSAMPLE = 100kHz fIN = 48.
PAGE 12
LTC1274/LTC1277 U U W U APPLICATIONS INFORMATION quency is shown in Figure 4. The ADCs have good distortion performance up to the Nyquist frequency and beyond. Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency.
PAGE 13
LTC1274/LTC1277 W U U UO APPLICATI S I FOR ATIO LTC1277 AIN+/AIN– Input Settling The input capacitor for the LTC1277 is switched onto the AIN+ input during the sample phase. The voltage on the AIN+ input must settle completely within the sample period. At the end of the sample phase the input capacitor switches to the AIN– input and the conversion starts. During the conversion the AIN+ input voltage is effectively “held” by the sample-and-hold and will not affect the conversion result.
PAGE 14
LTC1274/LTC1277 W U U UO APPLICATI S I FOR ATIO Figure 8. For bipolar mode, a 0.1µF ceramic provides adequate bypassing for the VSS pin. The capacitors must be located as close to the pins as possible. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. ground plane at AGND or as close as possible to the ADC. DGND (Pin 12) and all other analog grounds should be connected to this single analog ground point.
PAGE 15
LTC1274/LTC1277 W U U UO APPLICATI S I FOR ATIO DIGITAL INTERFACE The ADCs are designed to interface with microprocessors as a memory mapped device. The CS and RD control inputs are common to all peripheral memory interfacing. A separate CONVST is used to initiate a conversion. Figures 10a to 10c are the input/output characteristics of the ADCs. The code transitions occur midway between successive integer LSB values (i.e., 0.5LSB, 1.5LSB, 2.5LSB…FS – 1.5LSV). The output code is scaled such that 1.
PAGE 16
LTC1274/LTC1277 U W U UO APPLICATI S I FOR ATIO adjusted before full-scale error. Bipolar offset error adjustment is achieved by trimming the offset adjust while the input voltage is 0.5LSB below ground. This is done by applying an input voltage of – 0.50mV (– 0.5LSB) to the input in Figure 11c and adjusting the R8 until the ADC’s output code flickers between 0000 0000 0000 and 1111 1111 1111 in LTC1274 or between 0111 1111 1111 and 1000 0000 0000 in LTC1277.
PAGE 17
LTC1274/LTC1277 W U U UO APPLICATI S I FOR ATIO The narrow logic pulse on CONVST ensures that CONVST doesn’t return high during the conversion (see Note 13 following the Timing Characteristics table). In Mode 2 (Figure 15) CS is tied low. The falling edge of CONVST signal again starts the conversion. Data outputs both are in three-state until read by the MPU with the RD signal. Mode 2 can be used for operation with a shared MPU databus.
PAGE 18
LTC1274/LTC1277 W U U UO APPLICATI S I FOR ATIO CS = RD = 0 t16 HBEN (LTC1277) t12 tCONV (SAMPLE N) CONVST (SAMPLE N + 1) t7 t5 t5 BUSY t6 DATA (N – 1) DB11 TO DB0 LTC1274 DATA DATA N DB11 TO DB0 DATA (N + 1) DB11 TO DB0 t15 LTC1277 DATA DATA (N – 1) DB7 TO DB0 DATA (N – 1) DB11 TO DB8 DATA (N – 1) DB7 TO DB0 DATA N DB7 TO DB0 DATA N DB11 TO DB8 DATA N DB7 TO DB0 DATA (N + 1) DB7 TO DB0 LTC1274/77 • F14 Figure 14. Mode 1b. CONVST Starts a Conversion.
PAGE 19
LTC1274/LTC1277 W U U UO APPLICATI S I FOR ATIO t15 CS = 0 HBEN (LTC1277) t7 t18 tCONV (SAMPLE N) RD = CONVST (SAMPLE N + 1) t5 t10 BUSY t9 t6 LTC1274 DATA DATA (N – 1) DB11 TO DB0 LTC1277 DATA DATA (N – 1) DB7 TO DB0 DATA N DB11 TO DB0 DATA N DB7 TO DB0 DATA (N + 1) DB11 TO DB0 DATA N DB11 TO DB0 DATA N DB11 TO DB0 DATA N DB11 TO DB8 DATA (N + 1) DB7 TO DB0 DATA (N + 1) DB11 TO DB8 LTC1274/77 • F16 Figure 16.
PAGE 20
LTC1274/LTC1277 W U U UO APPLICATI S I FOR ATIO In the Sleep mode, the comparator of the ADC will start consuming power after the rising edge of SLEEP as shown in Figure 18a. If REFRDY is tied to NAP, the comparator will be powered up after REFRDY’s rising edge. Hence more power will be saved as in Figure 18b. 3ms (CREF = 4.7µF) 3ms (CREF = 4.7µF) SLEEP SLEEP REFRDY NAP = REFRDY COMPARATOR STATUS ON OFF ON COMPARATOR STATUS ON OFF ON LTC1274/77 • F18a Figure 18a.