Datasheet

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LTC1278

ESCRIPTIO

The LTC

1278 is a 1.6µs, 500ksps, sampling 12-bit A/D

converter that draws only 75mW from a single 5V or ±5V

supplies. This easy-to-use device comes complete with

a 200ns sample-and-hold, a precision reference and an

internally trimmed clock. Unipolar and bipolar conver-

sion modes add to the flexibility of the ADC. The low

power dissipation is made even more attractive by a

8.5mW power-down feature. Instant wake-up from shut-

down allows the converter to be powered down even

during brief inactive periods.

The LTC1278 converts 0V to 5V unipolar inputs from a

single 5V supply and ±2.5V bipolar inputs from ±5V

supplies. Maximum DC specs include ±1LSB INL and

±1LSB DNL. Outstanding guaranteed AC performance

includes 70dB S/(N + D) and 78dB THD at the input

frequency of 100kHz over temperature.

The internal clock is trimmed for 1.6µs conversion time.

The clock automatically synchronizes to each sample

command, eliminating problems with asynchronous clock

noise found in competitive devices. A separate convert

start input and a data ready signal (BUSY) ease connec-

tions to FIFOs, DSPs and microprocessors.

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Single Supply 5V or ±5V Operation

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Two Speed Grades,500ksps (LTC1278-5)

400ksps (LTC1278-4)

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70dB S/(N + D) and 74dB THD at Nyquist

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No Missing Codes Over Temperature

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75mW (Typ) Power Dissipation

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Power Shutdown with Instant Wake-Up

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Internal Reference Can Be Overdriven Externally

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Internal Synchronized Clock; No Clock Required

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High Impedance Analog Input

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0V to 5V or ±2.5V Input Range

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New Flexible, Friendly Parallel Interface to DSPs

and FIFOs

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24-Pin Narrow PDIP and SW Packages

12-Bit, 500ksps Sampling

A/D Converter with Shutdown

ITY

Effective Bits and Signal-to-(Noise + Distortion)

vs Input Frequency

INPUT FREQUENCY (Hz)

10k

EFFECTIVE NUMBER OF BITS

S/(N+D) (dB)

100k 1M 2M

LT1278 G4

SAMPLE

= 500kHz

NYQUIST

FREQUENCY

■

High Speed Data Acquisition

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Digital Signal Processing

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Multiplexed Data Acquisition Systems

■

Audio and Telecom Processing

■

Spectrum Analysis

, LTC and LT are registered trademarks of Linear Technology Corporation.

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REF

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AGND

D11(MSB)

D10

D9

D8

D7

D6

D5

D4

DGND

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BUSY

CS

RD

CONVST

SHDN

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D0

D1

D2

LTC1278-5

0.1µF

10µF

2.42V

REFERENCE

OUTPUT

ANALOG INPUT

(0V TO 5V)

10µF

0.1µF

12-BIT

PARALLEL

BUS

µP CONTROL

LINES

LTC1278 • TA01

CONVERSION START INPUT

POWER DOWN INPUT

Single 5V Supply, 500kHz, 12-Bit Sampling A/D Converter

Summary of content (16 pages)

PAGE 1
LTC1278 12-Bit, 500ksps Sampling A/D Converter with Shutdown U DESCRIPTIO FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Single Supply 5V or ±5V Operation Two Speed Grades,500ksps (LTC1278-5) 400ksps (LTC1278-4) 70dB S/(N + D) and 74dB THD at Nyquist No Missing Codes Over Temperature 75mW (Typ) Power Dissipation Power Shutdown with Instant Wake-Up Internal Reference Can Be Overdriven Externally Internal Synchronized Clock; No Clock Required High Impedance Analog Input 0V to 5V or ±2.
PAGE 2
LTC1278 U U PACKAGE/ORDER I FOR ATIO RATI GS W W W AVDD = DVDD = VDD (Notes 1, 2) Supply Voltage (VDD) .............................................. 12V Negative Supply Voltage (VSS) Bipolar Operation Only .......................... – 6V to GND Total Supply Voltage (VDD to VSS) Bipolar Operation Only ....................................... 12V Analog Input Voltage (Note 3) Unipolar Operation ................... – 0.3V to VDD + 0.3V Bipolar Operation............... VSS – 0.3V to VDD + 0.
PAGE 3
LTC1278 W U DY A IC ACCURACY (Note 5) LTC1278-4/LTC1278-5 MIN TYP MAX SYMBOL PARAMETER CONDITIONS S/(N + D) Signal-to-Noise Plus Distortion Ratio 100kHz Input Signal 250kHz Input Signal ● THD Total Harmonic Distortion First 5 Harmonics 100kHz Input Signal 250kHz Input Signal ● – 80 – 74 – 78 dB dB Peak Harmonic or Spurious Noise 100kHz Input Signal 250kHz Input Signal ● – 84 – 74 – 78 dB dB Intermodulation Distortion fIN1 = 99.37kHz, fIN2 = 102.4kHz fIN1 = 249.37kHz, fIN2 = 252.
PAGE 4
LTC1278 W U POWER REQUIRE E TS (Note 5) SYMBOL PARAMETER CONDITIONS LTC1278-4/LTC1278-5 MIN TYP MAX VDD Positive Supply Voltage (Notes 10, 11) Unipolar Bipolar 4.95 4.75 5.25 5.25 V V VSS Negative Supply Voltage (Note 10) Bipolar Only – 2.45 – 5.25 V IDD Positive Supply Current fSAMPLE = 500ksps SHDN = 0V ● ● 15.0 1.7 29.5 3.0 mA mA ISS Negative Supply Current fSAMPLE = 500ksps, VSS = – 5V ● 0.12 0.30 mA PD Power Dissipation fSAMPLE = 500ksps SHDN = 0V ● 75.0 8.
PAGE 5
LTC1278 WU TI I G CHARACTERISTICS (Note 5) The ● indicates specifications which apply over the full operating temperature range; all other limits and typicals TA = 25°C. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to ground with DGND and AGND wired together (unless otherwise noted).
PAGE 6
LTC1278 U W TYPICAL PERFORMANCE CHARACTERISTICS S/(N + D) vs Input Frequency and Amplitude AMPLITUDE (dB BELOW THE FUNDAMENTAL) VIN = 0dB 70 70 60 VIN = –20dB 50 40 30 20 VIN = –60dB 10 60 50 40 30 20 10 fSAMPLE = 500kHz 0 fSAMPLE = 500kHz 0 10k 100k 1M INPUT FREQUENCY (Hz) 1k 10M 1k 10k 100k 1M INPUT FREQUENCY (Hz) 10M LTC1278 G10 –60 –70 –40 –50 –60 2ND HARMONIC –70 –80 THD 3RD HARMONIC –90 –100 10k 100k INPUT FREQUENCY (Hz) 1M 2M 4000 –40 –60 –80 3500 3000 2500 2000 1500 1
PAGE 7
LTC1278 U U U PI FU CTIO S AIN (Pin 1): Analog Input. 0V to 5V (Unipolar), ±2.5V (Bipolar). RD (Pin 20): READ Input. This enables the output drivers when CS is low. VREF (Pin 2): 2.42V Reference Output. Bypass to AGND (10µF tantalum in parallel with 0.1µF ceramic). CS (Pin 21): The CHIP SELECT input must be low for the ADC to recognize CONVST and RD inputs. AGND (Pin 3): Analog Ground. BUSY (Pin 22): The BUSY output shows the converter status. It is low when a conversion is in progress.
PAGE 8
LTC1278 TEST CIRCUITS Load Circuits for Access Timing Load Circuits for Output Float Delay 5V 5V 3k 3k DBN DBN DBN 3k CL DBN 3k CL DGND 10pF DGND DGND DGND A) VOH TO HIGH-Z B) HIGH-Z TO VOL (t8) AND VOH TO VOL (t6) A) HIGH-Z TO VOH (t8) AND VOL TO VOH (t6) 10pF B) VOL TO HIGH-Z 1278 • TA08 LTC1278 TA08 WU W TI I G DIAGRA S CS to CONVST Setup Timing CS to RD Setup Timing SHDN to CONVST Wake-Up Timing CS CS SHDN t2 t1 t3 CONVST RD CONVST LTC1278 • TC02 LTC1278 • TC01 LTC1278
PAGE 9
LTC1278 U U W U APPLICATIONS INFORMATION compare mode. The input switch switches CSAMPLE to ground, injecting the analog input charge onto the summing junction. This input charge is successively compared with the binary-weighted charges supplied by the capacitive DAC. Bit decisions are made by the high speed comparator. At the end of a conversion, the DAC output balances the AIN input charge. The SAR contents (a 12-bit data word) which represent the AIN are loaded into the 12-bit output latches.
PAGE 10
LTC1278 U W U U APPLICATIONS INFORMATION 0 –10 fSAMPLE = 500kHz –20 –30 fSAMPLE = 500kHz fIN1 = 96.80kHz fIN2 = 101.68kHz –20 –40 –60 –80 –40 –100 –50 –60 –70 –80 THD 0 50k 100k 150k FREQUENCY (Hz) 200k 250k LTC1278 G8 3RD HARMONIC –90 –100 10k –120 2ND HARMONIC Figure 5. Intermodulation Distortion Plot 100k INPUT FREQUENCY (Hz) 1M 2M LT1278 G6 Figure 4.
PAGE 11
LTC1278 U W U UO APPLICATI S I FOR ATIO conversion starts. Any op amp that settles in 200ns to small current transients will allow maximum speed operation. If slower op amps are used, more settling time can be provided by increasing the time between conversions. Suitable devices capable of driving the ADC’s AIN input include the LT1360, LT1220, LT1223 and LT1224 op amps. INPUT RANGE ±2.58V (= ±1.033 × VREF) Internal Reference Figure 7. Supplying a 2.
PAGE 12
LTC1278 U W U UO APPLICATI S I FOR ATIO R1 50Ω ANALOG INPUT + V1 A1 – R2 10k FULL-SCALE ADJUST AGND LTC1278 F9a ANALOG INPUT 0V TO 5V 10k R9 20Ω R3 100k R7 100k LTC1278 R8 20k OFFSET ADJUST LTC1278 F9c Figure 9c. LTC1278 Bipolar Offset and Full-Scale Adjust Circuit AIN – 5V R5 4.3k FULL-SCALE 5V ADJUST –5V + R2 10k R4 100k R6 200Ω Figure 9a.
PAGE 13
LTC1278 W U U UO APPLICATI S I FOR ATIO Also, since any potential difference in grounds between the signal source and ADC appears as an error voltage in series with the input signal, attention should be paid to reducing the ground circuit impedances as much as possible. A single point analog ground separate from the logic system ground should be established with an analog ground plane at Pin 3 (AGND) or as close as possible to the ADC.
PAGE 14
LTC1278 W U U UO APPLICATI S I FOR ATIO power is off except the Internal Reference which is still active and provides 2.42V output voltage to the other circuitry. In this mode the ADC draws 8.5mW instead of 75mW (for minimum power, the logic inputs must be within 600mV of the supply rails). The wake-up time from the power shutdown to active state is 350ns. In mode 2 (Figure 14) CS is tied low. The falling CONVST signal again starts the conversion.
PAGE 15
LTC1278 W U U UO APPLICATI S I FOR ATIO t11 CS = 0 tCONV t4 SAMPLE N + 1 SAMPLE N CONVST t5 BUSY t7 t9 t10 RD t8 DATA N DB11 TO DB0 DATA DATA (N + 1) DB11 TO DB0 LTC1278 F14 Figure 14. Mode 2. CONVST Starts a Conversion. Data is Read by RD tCONV CS = 0 SAMPLE N SAMPLE N + 1 RD = CONVST t5 t9 BUSY t8 t6 DATA (N – 1) DB11 TO DB0 DATA DATA N DB11 TO DB0 DATA N DB11 TO DB0 DATA (N + 1) DB11-DB0 LTC1278 F15 Figure 15.
PAGE 16
LTC1278 U PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. N Package 24-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510) 1.265* (32.131) MAX 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 0.255 ± 0.015* (6.477 ± 0.381) 0.130 ± 0.005 (3.302 ± 0.127) 0.300 – 0.325 (7.620 – 8.255) 0.045 – 0.065 (1.143 – 1.651) 0.020 (0.508) MIN 0.009 – 0.015 (0.229 – 0.381) ( 0.125 (3.175) MIN +0.035 0.325 –0.015 +0.889 8.255 –0.381 0.065 (1.