Datasheet

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LTC1292/LTC1297

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FEATURES

DESCRIPTIO

KEY SPECIFICATIO S

TYPICAL APPLICATIO

Single Chip 12-Bit

Data Acquisition Systems

■

Resolution: 12 Bits

■

Fast Conversion Time: 12µs Max Over Temp

■

Low Supply Current: 6.0mA

■

Shutdown Supply Current: 5µA (LTC1297)

■

Single Supply 5V Operation

■

Power Shutdown After Each Conversion (LTC1297)

■

Built-In Sample-and-Hold

■

60kHz Maximum Throughput Rate (LTC1292)

■

Direct 3-Wire Interface to Most MPU Serial Ports and

All MPU Parallel Ports

■

Analog Inputs Common Mode to Supply Rails

The LTC

1292/LTC1297 are data acquisition systems that

contain a 12-bit, switched-capacitor successive approxi-

mation A/D, a differential input, sample-and-hold on the

(+) input, and serial I/O. When the LTC1297 is idle between

conversions it automatically powers down reducing the

supply current to 5µA, typically. The LTC1292 is capable

of digitizing signals at a 60kHz rate and with the device’s

excellent AC characteristics, it can be used for DSP appli-

cations. All these features are packaged in an 8-pin DIP

and are made possible using LTCMOS

switched-capaci-

tor technology.

The serial I/O is designed to communicate without external

hardware to most MPU serial ports and all MPU parallel

I/O ports allowing data to be transmitted over three wires.

Because of their accuracy, ease of use and small package

size these devices are well suited for digitizing analog

signals in remote applications where minimum number of

interconnects and power consumption are important.

12-Bit Differential Input Data Acquisition System

–

DIFFERENTIAL

INPUTS

COMMON MODE

RANGE

0V TO 5V

1N4148

REF

OUT

CLK

LTC1297

+IN

GND

–IN

LT1027

4.7µF

TANTALUM

8V TO 40V

1µF

22µF

TANTALUM

MC68HC11

SCK

MISO

*FOR OVERVOLTAGE PROTECTION LIMIT THE INPUT CURRENT TO 15mA

PER PIN OR CLAMP THE INPUTS TO V

AND GND WITH 1N4148 DIODES.

CONVERSION RESULTS ARE NOT VALID WHEN ANY INPUT IS OVERVOLTAGED

< GND OR V

> V

). SEE SECTION ON OVERVOLTAGE PROTECTION IN

THE APPLICATIONS INFORMATION.

LTC1292/7 TA01

SAMPLE

(Hz)

AVERAGE I

(µA)

100

1000

10000

1 100 10k

LTC1297• TA02

1k 100k

Power Supply Current

vs Sampling Frequency

, LTC and LT are registered trademarks of Linear Technology Corporation.

LTCMOS is trademark of Linear Technology Corporation

Summary of content (24 pages)

PAGE 1
LTC1292/LTC1297 Single Chip 12-Bit Data Acquisition Systems U FEATURES ■ ■ ■ ■ ■ ■ DESCRIPTIO Single Supply 5V Operation Power Shutdown After Each Conversion (LTC1297) Built-In Sample-and-Hold 60kHz Maximum Throughput Rate (LTC1292) Direct 3-Wire Interface to Most MPU Serial Ports and All MPU Parallel Ports Analog Inputs Common Mode to Supply Rails U KEY SPECIFICATIO S ■ ■ ■ ■ Resolution: 12 Bits Fast Conversion Time: 12µs Max Over Temp Low Supply Current: 6.
PAGE 2
LTC1292/LTC1297 U U RATI GS W W W W AXI U U ABSOLUTE PACKAGE/ORDER I FOR ATIO (Notes 1 and 2) Supply Voltage (VCC) to GND .................................. 12V Voltage Analog and Reference Inputs ..................................... –0.3V to VCC + 0.3V Digital Inputs ........................................ –0.3V to 12V Digital Outputs .......................... –0.3V to VCC + 0.3V Power Dissipation..............................................
PAGE 3
LTC1292/LTC1297 AC CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
PAGE 4
LTC1292/LTC1297 U DIGITAL A D DC ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
PAGE 5
LTC1292/LTC1297 U W TYPICAL PERFOR A CE CHARACTERISTICS LTC1297 Supply Current (Power Shutdown) vs CLK Frequency Unadjusted Offset Voltage vs Reference Voltage 25 0.9 10 5 0.7 0.6 0.5 0.4 VOS = 0.250mV 0.3 0.2 0.1 200 600 800 400 CLK FREQUENCY (kHz) 1000 3 2 4 REFERENCE VOLTAGE (V) 1 –0.4 –0.6 –0.8 –1.0 –1.2 2 3 4 REFERENCE VOLTAGE (V) 3 4 2 REFERENCE VOLTAGE (V) 0.5 0.4 0.3 0.2 0.1 0 –50 5 –25 25 50 75 100 0 AMBIENT TEMPERATURE (°C) VCC = 5V VREF = 5V CLK = 1MHz 0.4 0.3 0.2 0.
PAGE 6
LTC1292/LTC1297 U W TYPICAL PERFOR A CE CHARACTERISTICS Maximum Filter Resistor vs Cycle Time Maximum Clock Rate vs Source Resistance 10k 0.8 +VIN 0.6 RSOURCE + +IN – –IN 0.4 0.
PAGE 7
LTC1292/LTC1297 W BLOCK DIAGRA VCC 8 7 INPUT SHIFT REGISTER OUTPUT SHIFT REGISTER 2 +IN SAMPLE AND HOLD ANALOG INPUT MUX 3 –IN 6 CLK DOUT COMP 12-BIT SAR 12-BIT CAPACITIVE DAC 4 5 GND VREF CONTROL AND TIMING 1 CS LTC1292/7 BD TEST CIRCUITS Voltage Waveforms for DOUT Delay Time, tdDO On and Off Channel Leakage Current 5V CLK 0.8V ION tdDO ON CHANNEL A 2.4V IOFF A DOUT OFF CHANNEL 0.
PAGE 8
LTC1292/LTC1297 TEST CIRCUITS Voltage Waveforms for ten CS CLK B11 DOUT 0.8V ten U W U UO APPLICATI LTC1292/7 TC07 S I FOR ATIO The LTC1292/LTC1297 are data acquisition components which contain the following functional blocks: 1. 12-Bit Succesive Approximation Capacitive A/D Converter 2. Differential Input 3. Sample-and-Hold (S/H) 4. Synchronous, Half-Duplex Serial Interface 5.
PAGE 9
LTC1292/LTC1297 W U U UO APPLICATI S I FOR ATIO LTC1292 Operating Sequence tCYC CS CLK Hi-Z DOUT B11 B10 B9 B7 B8 tSMPL B6 B4 B5 B2 B3 B1 B0 B1 B3 B2 B4 B5 B6 B8 B7 B9 B10 B11 tSMPL tCONV LTC1292/7 AI01 LTC1297 Operating Sequence tCYC CS tsuCS POWER SHUTDOWN MODE CLK Hi-Z B11 B10 DOUT B9 B8 tSMPL B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 LTC1292/7 AI02 tCONV Microprocessor Interfaces The LTC1292/LTC1297 can interface directly (w
PAGE 10
LTC1292/LTC1297 W U U UO APPLICATI S I FOR ATIO LTC1292 CS MSB DO LOCATION #61 O O O O B11 B10 B9 B8 LOCATION #62 B7 B6 B5 B4 B3 B1 B0 BYTE 1 SCK CLK ANALOG INPUTS DOUT FROM LTC1292 STORED ON MC68HC11 RAM MC68HC11 DOUT MISO B2 BYTE 2 LTC1292/7 F02 Figure 2.
PAGE 11
LTC1292/LTC1297 W U U UO APPLICATI S I FOR ATIO LTC1297 ANALOG INPUTS DOUT FROM LTC1297 STORED ON MC68HC11 RAM MC68HC11 CS DO CLK SCK DOUT MISO MSB LOCATION #61 O O O O B11 B10 B9 B8 LOCATION #62 B7 B6 B5 B4 B3 B1 B0 B2 BYTE 1 BYTE 2 LTC1292/7 F04 Figure 4.
PAGE 12
LTC1292/LTC1297 W U U UO APPLICATI S I FOR ATIO LTC1292 LTC1297 ANALOG INPUTS DOUT FROM LTC1292/LTC1297 STORED IN 8051 RAM 8051 CS MSB P1.4 CLK P1.3 DOUT P1.1 R2 B11 B10 B9 B8 B7 B6 B5 B4 R3 B3 B2 B1 B0 O O O O B5 B4 B3 B1 B0 CS CLK DOUT B11 B10 B9 B8 B7 B6 B2 LTC1292/7 F05 Figure 5.
PAGE 13
LTC1292/LTC1297 U UO 1 W 2 U APPLICATI S I FOR ATIO 0 OUTPUT PORT SERIAL DATA MPU VCC 22µF TANTALUM 2-WIRE SERIAL INTERFACE TO OTHER PERIPHERALS OR LTC1292/LTC1297s 2 2 2 2 CS LTC1292 LTC1297 CS LTC1292 LTC1297 CS LTC1292 LTC1297 + + + – – 1 0.1µF 8 2 LTC1292 7 3 LTC1297 6 – 4 5 LTC1292/7 F06 Figure 6. Several LTC1292/LTC1297s Sharing One 2-Wire Serial Interface LTC1292/7 F07 Figure 7.
PAGE 14
LTC1292/LTC1297 W U U UO APPLICATI S I FOR ATIO Source Resistance The analog inputs of the LTC1292/LTC1297 look like a 100pF capacitor (CIN) in series with a 500Ω resistor (RON) (Figures 10a and 10b). CIN gets switched between (+) and (–) inputs once during each conversion cycle. Large external source resistors and capacitances will slow the settling of the inputs. It is important that the overall RC time constant is short enough to allow the analog inputs to settle completely within the allowed time.
PAGE 15
LTC1292/LTC1297 W U U UO APPLICATI S I FOR ATIO tWHCS CS CLK tSMPL (+) INPUT MUST SETTLE DURING THIS TIME DOUT B11 B10 B9 HI-Z 1ST BIT TEST (–) INPUT MUST SETTLE DURING THIS TIME (+) INPUT (–) INPUT LTC1292/7 F11b Figure 11b. Setup Time (tsuCS) Is Met for the LTC1292 tWHCS CS CLK tSMPL (+) INPUT MUST SETTLE DURING THIS TIME DOUT B11 B10 HI-Z 1ST BIT TEST (–) INPUT MUST SETTLE DURING THIS TIME (+) INPUT (–) INPUT LTC1292/7 F11c Figure 11c.
PAGE 16
LTC1292/LTC1297 W U U UO APPLICATI S I FOR ATIO tWHCS tsuCS CS CLK DOUT tSMPL (+) INPUT MUST SETTLE DURING THIS TIME B11 B10 HI-Z 1ST BIT TEST (–) INPUT MUST SETTLE DURING THIS TIME (+) INPUT (–) INPUT LTC1292/7 F12 Input Op Amps When driving the analog inputs with an op amp it is important that the op amp settles within the allowed time (see Figures 11a, 11b, 11c and 12). Again the “+” and “– ” input sampling times can be extended as described above to accommodate slower op amps.
PAGE 17
LTC1292/LTC1297 U W U UO APPLICATI S I FOR ATIO RC Input Filtering It is possible to filter the inputs with an RC network as shown in Figure 15. For large values of CF (e.g., 1µF) the capacitive input switching currents are averaged into a net DC current. A filter should be chosen with a small resistor and large capacitor to prevent DC drops across the resistor. The magnitude of the DC current is approximately IDC = 100pF × VIN/tCYC and is roughly proportional to VIN.
PAGE 18
LTC1292/LTC1297 W U U UO APPLICATI S I FOR ATIO switching currents due to the switched-capacitor conversion technique (see Figure 16). During each bit test of the conversion (every CLK cycle) a capacitive current spike will be generated on the reference pin by the A/D. These current spikes settle quickly and do not cause a problem.
PAGE 19
LTC1292/LTC1297 W U U UO APPLICATI S I FOR ATIO is reduced. The typical performance characteristics curve of Noise Error vs Reference Voltage shows the LSB contribution of this 200µV of noise. For operation with a 5V reference, the 200µV noise is only 0.16LSB peak-to-peak. Here the LTC1292/LTC1297 noise will contribute virtually no uncertainty to the output code. For reduced references, the noise may become a significant fraction of an LSB and cause undesirable jitter in the output code.
PAGE 20
LTC1292/LTC1297 U UO S I FOR ATIO 0 0 –20 –20 –40 –40 MAGNITUDE (dB) MAGNITUDE (dB) W U APPLICATI –60 –80 –60 –80 –100 –100 –120 –120 –140 –140 0 20 15 10 FREQUENCY (kHz) 5 30 25 LTC1292/7 F20a Figure 20a. fIN = 1kHz, fS = 58.8kHz, SNR = 73.0dB 0 –20 MAGNITUDE (dB) –40 –60 –80 –100 –120 –140 0 20 15 10 FREQUENCY (kHz) 5 30 25 LTC1292/7 F20b Figure 20b. fIN = 28kHz, fS = 58.8kHz, SNR = 61.5dB 12.0 fS = 58.8kHz EFFECTIVE NUMBER OF BITS 11.5 11.0 10.5 10.0 9.5 9.0 8.5 8.
PAGE 21
LTC1292/LTC1297 W U U UO APPLICATI S I FOR ATIO If VCC and VREF are not tied together, then VCC should be turned on first, then VREF. If this sequence cannot be met, connecting a diode from VREF to VCC is recommended (see Figure 25). Because a unique input protection structure is used on the digital input pins, the signal levels on these pins can exceed the device VCC without damaging the device.
PAGE 22
LTC1292/LTC1297 W U U UO APPLICATI S I FOR ATIO A “Quick Look” Circuit for the LTC1292 Users can get a quick look at the function and timing of the LTC1292 by using the “Quick Look” circuit in Figure 26. VREF is tied to VCC. VIN is applied to the +IN input and the –IN input is tied to the ground plane. CS is driven at 1/32 the clock rate by the CD4520 and DOUT outputs the data.
PAGE 23
LTC1292/LTC1297 W U U UO APPLICATI S I FOR ATIO Opto-Isolated Temperature Monitor Amplification of sensor outputs is often required to generate a signal large enough to be properly digitized. For example, a J-type thermocouple provides only 52µV/°C. The 5µV offset of the LTC1050 chopper op amp generates less than 0.1°C error (Figure 31). Cold junction compensation is provided by the LT1025A. (For more detail see LTC Design Note 5). In the opto-isolated interface two signals are generated from one.
PAGE 24
LTC1292/LTC1297 U PACKAGE DESCRIPTIO J8 Package 8-Lead CERDIP (Narrow .300 Inch, Hermetic) (Reference LTC DWG # 05-08-1110) 0.300 BSC (0.762 BSC) 0.200 (5.080) MAX CORNER LEADS OPTION (4 PLCS) 0.008 – 0.018 (0.203 – 0.457) 0° – 15° 0.023 – 0.045 (0.584 – 1.143) HALF LEAD OPTION 0.045 – 0.068 (1.143 – 1.727) FULL LEAD OPTION 0.015 – 0.060 (0.381 – 1.524) 0.405 (10.287) MAX 0.005 (0.127) MIN 8 NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE OR TIN PLATE LEADS 0.014 – 0.026 (0.360 – 0.660) 5 0.