Datasheet

12
LTC1292/LTC1297
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Figure 5. Hardware and Software Interface to Intel 8051 Processor
LABEL MNEMONIC OPERAND COMMENTS
MOV P1,#02h BIT 1 PORT 1 SET AS INPUT
CLR P1.3 CLK GOES LOW
SETB P1.4 CS GOES HIGH
CONT CLR P1.4 CS GOES LO
NOP 4 NOP FOR LTC1297 t
suCS
(Wakeup
NOP Time) (Not Needed for LTC1292)
NOP
NOP
SETB P1.3 CLK GOES HIGH
CLR P1.3 CLK GOES LOW
SETB P1.3 CLK GOES HIGH
CLR P1.3 CLK GOES LOW
MOV R4,#08H LOAD COUNTER
LOOP MOV C,P1.1 READ DATA BIT INTO CARRY
RLC A ROTATE DATA BIT INTO ACC
SETB P1.3 CLK GOES HIGH
CLR P1.3 CLK GOES LOW
DJNZ R4,LOOP NEXT BIT
MOV R2,A STORE MSBs IN R2
MOV C,P1.1 READ DATA BIT INTO CARRY
CLR A CLEAR ACC
RLC A ROTATE DATA BIT (B3) INTO ACC
SETB P1.3 CLK GOES HIGH
CLR P1.3 CLK GOES LOW
MOV C,P1.1 READ DATA BIT INTO CARRY
RLC A ROTATE DATA BIT (B2) INTO ACC
SETB P1.3 CLK GOES HIGH
CLR P1.3 CLK GOES LOW
MOV C,P1.1 READ DATA BIT INTO CARRY
RLC A ROTATE DATA BIT (B1) INTO ACC
SETB P1.3 CLK GOES HIGH
CLR P1.3 CLK GOES LOW
MOV C,P1.1 READ DATA BIT INTO CARRY
SETB P1.4 CS GOES HIGH
RRC A ROTATE DATA BIT (B0) INTO ACC
RRC A ROTATE RIGHT INTO ACC
RRC A ROTATE RIGHT INTO ACC
RRC A ROTATE RIGHT INTO ACC
MOV R3,A STORE LSBs IN R3
AJMP CONT START NEXT CONVERSION
LABEL MNEMONIC OPERAND COMMENTS
8051 CODE
Sharing the Serial Interface
The LTC1292/LTC1297 can share the same two-wire
serial interface with other peripheral components or other
LTC1292/LTC1297s (Figure 6). In this case, the CS signals
decide which LTC1292 is being addressed by the MPU.
ANALOG CONSIDERATIONS
Grounding
The LTC1292/LTC1297 should be used with an analog
ground plane and single point grounding techniques. Do
not use wire wrapping techniques to breadboard and
evaluate the device. To achieve the optimum performance
D
OUT
FROM LTC1292/LTC1297 STORED IN 8051 RAM
B3
B2
B0
B1
OO
OO
R3
B7
B6
B5
B4
B10 B9 B8B11
R2
MSB
ANALOG
INPUTS
CLK
D
OUT
LTC1292
LTC1297
CS
P1.4
P1.3
P1.1
8051
LTC1292/7 F05
CS
D
OUT
B11
B7
B8
B9
B10
B4
B5B6
B3
B2
B1
B0
CLK