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LTC1293/LTC1294/LTC1296

129346fs

Single Chip 12-Bit

Data Acquisition System

The LTC1293/4/6 is a family of data acquisition systems

which contain a serial I/O successive approximation A/D

converter. It uses LTCMOS

switched capacitor technol-

ogy to perform either 12-bit unipolar, or 11-bit plus sign

bipolar A/D conversions. The input multiplexer can be

configured for either single ended or differential inputs (or

combinations thereof). An on-chip sample and hold is

included for all single ended input channels. When the

LTC1293/4/6 is idle it can be powered down in applica-

tions where low power consumption is desired. The

LTC1296 includes a System Shutdown Output pin which

can be used to power down external circuitry, such as

signal conditioning circuitry prior to the input mux.

The serial I/O is designed to communicate without external

hardware to most MPU serial ports and all MPU parallel

I/O ports allowing up to eight channels of data to be

transmitted over as few as three wires.

ESCRIPTIO

■

Software Programmable Features

Unipolar/Bipolar Conversion

Differential/Single Ended Inputs

MSB-First or MSB/LSB Data Sequence

Power Shutdown

■

Built-In Sample and Hold

■

Single Supply 5V or ±5V Operation

■

Direct 4-Wire Interface to Most MPU Serial

Ports and All MPU Parallel Ports

■

46.5kHz Maximum Throughput Rate

■

System Shutdown Output (LTC1296)

ITY

12-Bit Data Acquisition System with Power Shutdown

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

COM

DGND

–

5.1k

1.2M

10k

1/4 LT1014

1.2M

1µF

350Ω STRAIN

GAUGE BRIDGE

+5V

47µF

1N4148

MPU

LTC1296

SSO

CLK

OUT

REF

–

AGND

–

THREE ADDITIONAL STRAIN GAUGE INPUTS

CAN BE ACCOMMODATED USING THE OTHER

AMPLIFIERS IN THE LT1014

LTC1293 TA01

2N3906

74HC04

■

Resolution: 12 Bits

■

Fast Conversion Time: 12µs Max Over Temp

■

Low Supply Current: 6.0mA

LTCMOS

is a trademark of Linear Technology Corporation

KEY SPECIFICATIO S

Summary of content (28 pages)

PAGE 1
LTC1293/LTC1294/LTC1296 Single Chip 12-Bit Data Acquisition System U DESCRIPTIO FEATURES ■ ■ ■ ■ ■ ■ Software Programmable Features Unipolar/Bipolar Conversion Differential/Single Ended Inputs MSB-First or MSB/LSB Data Sequence Power Shutdown Built-In Sample and Hold Single Supply 5V or ±5V Operation Direct 4-Wire Interface to Most MPU Serial Ports and All MPU Parallel Ports 46.
PAGE 2
LTC1293/LTC1294/LTC1296 W W W AXI U U ABSOLUTE RATI GS (Notes 1 and 2) Supply Voltage (VCC) to GND or V – ......................... 12V Negative Supply Voltage (V –) ..................... –6V to GND Voltage Analog and Reference Inputs ............................ (V –) –0.3V to VCC + 0.3V Digital Inputs ......................................... –0.3V to 12V Digital Outputs .......................... –0.3V to VCC + 0.
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LTC1293/LTC1294/LTC1296 W U U CO VERTER A D ULTIPLEXER CHARACTERISTICS PARAMETER CONDITIONS TYP MAX UNITS Offset Error (Note 4) ● ±3.0 ±3.0 ±3.0 LSB Linearity Error (INL) (Notes 4, 5) ● ±0.5 ±0.5 ±0.75 LSB Gain Error (Note 4) ● ±0.5 ±1.0 ±4.0 LSB ● 12 12 12 Bits LTC1293/4/6B Minimum Resolution for which No Missing Codes are Guaranteed MIN TYP MAX (Note 3) LTC1293/4/6C MIN TYP MAX LTC1293/4/6D MIN (V –)–0.05V to VCC + 0.
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LTC1293/LTC1294/LTC1296 U DIGITAL A D DC ELECTRICAL CHARACTERISTICS (Note 3) LTC1293/4/6B LTC1293/4/6C LTC1293/4/6D MIN TYP MAX SYMBOL PARAMETER CONDITIONS VIH High Level Input Voltage VCC = 5.25V ● VIL Low Level Input Voltage VCC = 4.75V ● 0.8 V IIH High Level Input Current VIN = VCC ● 2.5 µA IIL Low Level Input Current VIN = 0V ● –2.5 µA VOH High Level Output Voltage VCC = 4.75V, IO = –10mA IO = 360µA ● 2.0 2.4 UNITS V 4.7 4.0 V VOL Low Level Output Voltage VCC = 4.
PAGE 5
LTC1293/LTC1294/LTC1296 U W TYPICAL PERFOR A CE CHARACTERISTICS Supply Current vs Supply Voltage Unadjusted Offset Voltage vs Reference Voltage Supply Current vs Temperature 10 CLK = 1MHz TA = 25°C 0.9 VCC = 5V CLK = 1MHz VCC = 5V 9 0.8 OFFSET (LSB = 1/4096 × VREF) 10 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 8 6 4 8 7 6 5 2 5 4 6 SUPPLY VOLTAGE (V) 0.1 Change in Gain vs Reference Voltage 0.75 0.50 0.25 VCC = 5V –0.2 –0.4 LTC1294/6 –0.6 –0.8 –1.
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LTC1293/LTC1294/LTC1296 U W TYPICAL PERFOR A CE CHARACTERISTICS Maximum Clock Rate vs Source Resistance 10k 1.0 250 VCC = 5V VREF = 5V CLK = 1MHz MAXIMUM CLK FREQUENCY* (MHz) MSB FIRST DATA 150 LSB FIRST DATA 100 50 0 –50 –25 25 50 75 100 0 AMBIENT TEMPERATURE (°C) 0.8 +VIN 0.6 RSOURCE– 1k 10k RSOURCE – (Ω) RSOURCE+ + – 1 100 1000 RSOURCE+ (Ω) 10 10 LTC1293 G12 Noise Error vs Reference Voltage 2.
PAGE 7
LTC1293/LTC1294/LTC1296 U U U PI FU CTIO S LTC1293 # PIN FUNCTION 1–6 7 CH0 – CH5 COM Analog Inputs Common 8 9 10 11 12 13 14 15 16 DGND V– AGND VREF DIN DOUT CS CLK VCC DESCRIPTION The analog inputs must be free of noise with respect to AGND. The common pin defines the zero reference point for all single ended inputs. It must be free of noise and is usually tied to the analog ground plane. Digital Ground This is the ground for the internal logic. Tie to the ground plane.
PAGE 8
LTC1293/LTC1294/LTC1296 W BLOCK DIAGRA (Pin numbers refer to LTC1294) 18 20 DVCC AVCC 19 INPUT SHIFT REGISTER 15 DIN CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM OUTPUT SHIFT REGISTER 16 CLK DOUT 1 SAMPLE AND HOLD 2 3 4 5 COMP ANALOG INPUT MUX 12-BIT SAR 6 12-BIT CAPACITIVE DAC 7 8 9 11 10 12 V– DGND AGND CONTROL AND TIMING 14 13 REF – REF + 17 CS LTC1293 BD TEST CIRCUITS Load Circuit for tdDO, tr and tf Load Circuit for tenSSO and tdisSSO 1.4V 1.
PAGE 9
LTC1293/LTC1294/LTC1296 TEST CIRCUITS Voltage Waveforms for ten CS DIN START 4 3 2 1 CLK 6 5 7 8 0.8V DOUT B11 ten LTC1293 TC07 Voltage Waveform for tdisSSO CS Voltage Waveform for DOUT Rise and Fall Times, tr, tf 2.4V DOUT 0.8V tdisSSO 0.4V tr 2.4V SSO tf LTC1293 TC04 LTC1293 TC10 Voltage Waveform for for tenSSO CLK Voltage Waveform for tdis 2.0V CS 0.8V tenSSO DOUT WAVEFORM 1 (SEE NOTE 1) SSO 90% tdis 0.
PAGE 10
LTC1293/LTC1294/LTC1296 U W U UO APPLICATI S I FOR ATIO The LTC 1293/4/6 is a data acquisition component which contains the following functional blocks: 1. 12-bit successive approximation capacitive A/D converter 2. Analog multiplexer (MUX) 3. Sample and hold (S/H) 4. Synchronous, half duplex serial interface 5.
PAGE 11
LTC1293/LTC1294/LTC1296 W U U UO APPLICATI S I FOR ATIO Table 1a.
PAGE 12
LTC1293/LTC1294/LTC1296 W U U UO APPLICATI S I FOR ATIO Bipolar Transfer Curve (UNI = 0) OUTPUT CODE INPUT VOLTAGE INPUT VOLTAGE (VREF = 5V) OUTPUT CODE INPUT VOLTAGE INPUT VOLTAGE (VREF = 5V) 011111111111 011111111110 • • • 000000000001 000000000000 VREF – 1LSB VREF – 2LSB • • • 1LSB 0V 4.9976V 4.9851V • • • 0.0024V 0V 111111111111 111111111110 • • • 100000000001 100000000000 –1LSB –2LSB • • • –(VREF) + 1LSB – (VREF) –0.0024V –0.0048V • • • –4.9976V –5.
PAGE 13
LTC1293/LTC1294/LTC1296 W U U UO APPLICATI S I FOR ATIO Example 2: The same conditions as Example 1 except COM = 1V. The resulting input span is 1V ≤ IN + ≤ 4V. Note if IN + ≥ 4V the resulting DOUT word is all 1’s. If IN + ≤ 1V then the resulting DOUT word is all 0’s. Example 3: Let VCC = 5V, V – = –5V, REF+ = 4V, REF – = 1V and COM = 1V. Bipolar mode of operation. The resulting input span is –2V ≤ IN + ≤ 4V.
PAGE 14
LTC1293/LTC1294/LTC1296 W U U UO APPLICATI S I FOR ATIO Power Shutdown Operating Sequence Example: Differential Inputs (CH4 +, CH5 –), Unipolar Mode and MSB-First Data REQUEST POWER SHUTDOWN CS NEW CONVERSION BEGINS SHUTDOWN* CLK START SEL1 UNI START PS DIN SEL1 UNI SEL1/ ODD/ SEL0 MSBF DIFF SIGN HI-Z DOUT B11 • • • • • • • • • PS MSBF DON'T CARE • B0 FILLED WITH ZEROES HI-Z SEL1/ ODD/ SEL0 DIFF SIGN LTC1293 AI06 *STOPPING THE CLOCK WILL HELP REDUCE POWER CONSUMPTION.
PAGE 15
LTC1293/LTC1294/LTC1296 W U U UO APPLICATI S I FOR ATIO Motorola SPI (MC68HC11) The MC68HC11 has been chosen as an example of an MPU with a dedicated serial port. This MPU transfers data MSBfirst and in 8-bit increments. The DIN word sent to the data register starts the SPI process. With three 8-bit transfers, the A/D result is read into the MPU. The second 8-bit transfer clocks B11 through B8 of the A/D conversion result into the processor.
PAGE 16
LTC1293/LTC1294/LTC1296 UO U OPERAND #$50 $1028 #$1B $1009 #$10 $50 #$E0 $51 #$00 $52 #$1000 $08,X,$01 $50 $102A $1029 WAIT1 $51 COMMENTS CONFIGURATION DATA FOR SPCR LOAD DATA INTO SPCR ($1028) CONFIG.
PAGE 17
LTC1293/LTC1294/LTC1296 W U U UO APPLICATI S I FOR ATIO 8051 CODE LABEL MNEMONIC SETB CONT MOV CLR MOV LOOP1 RLC CLR MOV SETB DJNZ MOV CLR MOV LOOP MOV RLC SETB CLR DJNZ MOV MOV SETB OPERAND P1.4 A,#87H P1.4 R4,#08H A P1.3 P1.2,C P1.3 R4,LOOP1 P1,#04H P1.3 R4,#09H C,P1.2 A P1.3 P1.3 R4,LOOP R2,A C,P1.2 P1.3 COMMENTS CS GOES HIGH DIN WORD FOR LTC1294 CS GOES LOW LOAD COUNTER ROTATE DIN BIT INTO CARRY CLK GOES LOW OUTPUT DIN BIT TO LTC1294 CLK GOES HIGH NEXT DIN BIT P1.
PAGE 18
LTC1293/LTC1294/LTC1296 W U U UO APPLICATI S I FOR ATIO VERTICAL: 0.5mV/DIV LTC1294. Figure 4 shows an example of an ideal LTC1293/ 4/6 ground plane design for a two sided board. Of course this much ground plane will not always be possible, but users should strive to get as close to this ideal as possible. HORIZONTAL: 10µs/DIV VCC 22µF TANTALUM Figure 5. Poor VCC Bypassing. Noise and Ripple Can Cause A/D Errors.
PAGE 19
LTC1293/LTC1294/LTC1296 W U U UO APPLICATI S I FOR ATIO Source Resistance The analog inputs of the LTC1293/4/6 look like a 100pF capacitor (CIN) in series with a 500Ω resistor (RON). CIN gets switched between (+) and (–) inputs once during each conversion cycle. Large external source resistors and capacitances will slow the settling of the inputs. It is important that the overall RC time constant is short enough to allow the analog inputs to settle completely within the allowed time.
PAGE 20
LTC1293/LTC1294/LTC1296 U W U UO APPLICATI S I FOR ATIO VERTICAL: 5mV/DIV within the minimum settling windows of 2.5µs (“+” input) and 1µs(“–” input) that occurs at the maximum clock rate of 1MHz. Figures 9 and 10 show examples of adequate and poor op amp settling. HORIZONTAL: 500ns/DIV the cycle time as shown in the typical performance characteristic curve Maximum Filter Resistor vs Cycle Time.
PAGE 21
LTC1293/LTC1294/LTC1296 W U U UO APPLICATI Usually VERROR will not be significant. For a 60Hz signal on the “–” input to generate a 0.25LSB error (300µV) with the converter running at CLK = 1MHz, its peak value would have to be 66mV. Rearranging the above equation the maximum sinusoidal signal that can be digitized to a given accuracy is given as: Reference Input The voltage on the reference input of the LTC1293/4/6 determines the voltage span of the A/D converter.
PAGE 22
LTC1293/LTC1294/LTC1296 U W U UO APPLICATI S I FOR ATIO a 1.25 reference. If this offset is unacceptable, it can be corrected digitally by the receiving system or by offsetting the “–” input to the LTC1293/4/6. Noise with Reduced VREF The total input referred noise of the LTC1293/4/6 can be reduced to approximately 200µV peak-to-peak using a ground plane, good bypassing, good layout techniques and minimizing noise on the reference inputs.
PAGE 23
LTC1293/LTC1294/LTC1296 U UO S I FOR ATIO 0 0 –20 –20 –40 –40 MAGNITUDE (dB) MAGNITUDE (dB) W U APPLICATI –60 –80 –80 –100 –100 –120 –120 –140 –140 0 5 10 20 15 FREQUENCY (kHz) 25 1293 F16a 0 5 10 15 FREQUENCY (kHz) 20 25 1293 F8 Figure 18. LTC1294 FFT Plot fIN1 = 5.1kHz, fIN2 = 5.6kHz, fS = 45.4kHz with ±5V Supplies Figure 16a. LTC1294 FFT Plot fIN = 1kHz, fS = 45.4kHz, SNR = 72.7dB with ±5V Supplies For +5V supplies the ENOB decreases more rapidly.
PAGE 24
LTC1293/LTC1294/LTC1296 W U U UO APPLICATI S I FOR ATIO This means four channels can handle 7mA of input current each. Reducing CLK frequency from a maximum of 1MHz (See typical performance characteristics curves Maximum CLK Frequency vs Source Resistance and Sample and Hold Acquisition Time vs Source Resistance) allows the use of larger current limiting resistors.
PAGE 25
LTC1293/LTC1294/LTC1296 W U U UO APPLICATI S I FOR ATIO Unipolar conversion is requested and the data is output MSB first. CS is driven at 1/64 the clock rate by the CD4520 and DOUT outputs the data. The output data from the DOUT pin can be viewed on an oscilloscope that is set up to trigger on the falling edge of CS (Figure 24). A “Quick Look” Circuit for the LTC1294/6 Users can get a quick look at the function and timing of the LTC1294/6 by using the following simple circuit (Figure 23).
PAGE 26
LTC1293/LTC1294/LTC1296 UO TYPICAL APPLICATI S Micropower, 5000V Opto-Isolated, Multichannel,12-Bit Data Acquisition System is Accessed Once Every Two Seconds 4N28s 10k 9V 5V 10k 2N3906 LT1027 10k C1 2N3906 51k 150Ω 5V 10k 10µF* SCK 150Ω 51k 5V 8 ANALOG INPUTS 0–5V RANGE CH0 DVCC CH1 AVCC CH2 CLK CH3 CS CH4 DOUT LTC1294 CH5 DIN CH6 REF+ CH7 REF – COM AGND DGND 5.1k (3) 10k C0 150Ω 51k TO 68HC11 5V 10k 51k MOSI 150Ω TO ADDITIONAL LTC1294s 5.
PAGE 27
LTC1293/LTC1294/LTC1296 U PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. J Package 20-Lead Ceramic DIP 0.290 - 0.320 (7.366 - 8.128) GLASS SEALANT 1.060 (26.924) MAX 0.160 (4.064) MAX 20 0.015 – 0.060 (0.381 – 1.524) 19 18 17 16 15 14 13 12 11 2 3 4 5 6 7 8 9 10 0.200 (5.080) 0.220 - 0.310 0.025 MAX (5.588 - 7.874) (0.635) RAD TYP 0° – 15° 1 0.008 – 0.018 (0.203 – 0.457) 0.038 – 0.068 (0.965 – 1.727) 0.125 (3.175) MIN 0.385 ± 0.025 (9.779 ± 0.
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LTC1293/LTC1294/LTC1296 U PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. S Package 16-Lead Plastic SOL 0.398 – 0.413 (10.109 – 10.490) 0.291 – 0.299 (7.391 – 7.595) 0.005 (0.127) RAD MIN 0.037 – 0.045 (0.940 – 1.143) 0.093 – 0.104 (2.362 – 2.642) 0.010 – 0.029 × 45° (0.254 – 0.737) 16 15 14 13 12 10 11 9 0° – 8° TYP 0.009 – 0.013 (0.229 – 0.330) 0.050 (1.270) TYP SEE NOTE 0.016 – 0.050 (0.406 – 1.270) 0.394 – 0.419 (10.008 – 10.643) 0.004 – 0.