Datasheet

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LTC1286/LTC1298

Micropower Sampling

12-Bit A/D Converters In

S0-8 Packages

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12-Bit Resolution

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8-Pin SOIC Plastic Package

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Low Cost

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Low Supply Current: 250µA Typ.

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Auto Shutdown to 1nA Typ.

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Guaranteed ±3/4LSB Max DNL

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Single Supply 5V to 9V Operation

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On-Chip Sample-and-Hold

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60µs Conversion Time

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Sampling Rates:

12.5 ksps (LTC1286)

11.1 ksps (LTC1298)

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I/O Compatible with SPI, Microwire, etc.

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Differential Inputs (LTC1286)

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2-Channel MUX (LTC1298)

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3V Versions Available: LTC1285/LTC1288

The LTC1286/LTC1298 are micropower, 12-bit, succes-

sive approximation sampling A/D converters. They typi-

cally draw only 250µA of supply current when converting

and automatically power down to a typical supply current

of 1nA whenever they are not performing conversions.

They are packaged in 8-pin SO packages and operate on

5V to 9V supplies. These 12-bit, switched-capacitor, suc-

cessive approximation ADCs include sample-and-holds.

The LTC1286 has a single differential analog input. The

LTC1298 offers a software selectable 2-channel MUX.

On-chip serial ports allow efficient data transfer to a wide

range of microprocessors and microcontrollers over three

wires. This, coupled with micropower consumption, makes

remote location possible and facilitates transmitting data

through isolation barriers.

These circuits can be used in ratiometric applications or

with an external reference. The high impedance analog

inputs and the ability to operate with reduced spans (to

1.5V full scale) allow direct connection to sensors and

transducers in many applications, eliminating the need for

gain stages.

5V4.7µF

ANALOG INPUT

–IN

GND

CLK

OUT

REF

LTC1286

MPU

(e.g., 8051)

P1.4

P1.3

P1.2

+IN

0V TO 5V RANGE

LTC1286/98 • TA01

CS/SHDN

SERIAL DATA LINK

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Battery-Operated Systems

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Remote Data Acquisition

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Battery Monitoring

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Handheld Terminal Interface

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Temperature Measurement

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Isolated Data Acquisition

SAMPLE FREQUENCY (Hz)

0.1k

SUPPLY CURRENT (µA)

100

1000

1k 10k 100k

LTC1286/98 • TA02

= 25°C

= V

REF

= 5V

CLK

= 200kHz

DESCRIPTION

25µW, S0-8 Package, 12-Bit ADC

Samples at 200Hz and Runs Off a 5V Supply

Supply Current vs Sample Rate

FEATURES

APPLICATIONS

TYPICAL APPLICATIONS N

Summary of content (24 pages)

PAGE 1
LTC1286/LTC1298 Micropower Sampling 12-Bit A/D Converters In S0-8 Packages DESCRIPTION U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ The LTC1286/LTC1298 are micropower, 12-bit, successive approximation sampling A/D converters. They typically draw only 250µA of supply current when converting and automatically power down to a typical supply current of 1nA whenever they are not performing conversions. They are packaged in 8-pin SO packages and operate on 5V to 9V supplies.
PAGE 2
LTC1286/LTC1298 W W W ABSOLUTE MAXIMUM RATINGS (Notes 1 and 2) Supply Voltage (VCC) to GND ................................... 12V Voltage Analog and Reference ................ –0.3V to VCC + 0.3V Digital Inputs ......................................... –0.3V to 12V Digital Output ............................. –0.3V to VCC + 0.3V Power Dissipation .............................................. 500mW Operating Temperature Range LTC1286C/LTC1298C.............................
PAGE 3
LTC1286/LTC1298 W U U CONVERTER AND MULTIPLEXER CHARACTERISTICS PARAMETER CONDITIONS Resolution (No Missing Codes) MIN ● LTC1286 TYP MAX 12 (Note 5) LTC1298 TYP MAX MIN 12 UNITS Bits ● ±3/4 ±2 ±3/4 ±2 Differential Linearity Error ● ±1/4 ±3/4 ±1/4 ±3/4 LSB Offset Error ● 3/4 ±3 3/4 ±3 LSB Gain Error ● ±2 ±2 ±8 LSB Integral Linearity Error (Note 6) Analog Input Range (Note 7 and 8) REF Input Range (LTC1286) (Notes 7, 8, and 9) 4.5 ≤ VCC ≤ 5.5V 5.
PAGE 4
LTC1286/LTC1298 AC CHARACTERISTICS (Note 5) SYMBOL PARAMETER CONDITIONS tSMPL Analog Input Sample Time See Operating Sequence MIN TYP MAX 1.5 ● ● UNITS CLK Cycles fSMPL (MAX) Maximum Sampling Frequency LTC1286 LTC1298 12.5 11.
PAGE 5
LTC1286/LTC1298 U W TYPICAL PERFORMANCE CHARACTERISTICS Reference Current vs Sample Rate (LTC1286) 100 70 60 50 40 30 20 CHANGE IN OFFSET (LSB = 1/4096 VREF) VCC = VREF = 5V fSMPL = 12.5kHz fCLK = 200kHz TA = 25°C 94.5 REFERENCE CURRENT (µA) REFERENCE CURRENT (µA) 80 3 95 TA = 25°C VCC = 5V VREF = 5V fCLK = 200kHz 90 94 93.5 93 92.5 10 0 0 2 4 8 6 10 FREQUENCY (kHz) 12 92 –55 –35 –15 14 -1 1.5 -2 VCC = VREF = 5V fCLK = 200kHz fSMPL = fSMPL (MAX) 65 –0.4 –8 –0.3 –.25 –0.2 –0.
PAGE 6
LTC1286/LTC1298 U W TYPICAL PERFORMANCE CHARACTERISTICS Spurious Free Dynamic Range vs Frequency 100 0 80 90 80 70 60 50 40 30 20 TA = 25°C VCC = VREF = 5V fSMPL = 12.5kHz 10 0 10k 100k INPUT FREQUENCY (Hz) 1k TA = 25°C VCC = VREF = 5V fIN = 1kHz fSMPL = 12.5kHz 70 60 20 50 40 30 20 30 40 50 60 70 80 10 TA = 25°C VCC = VREF = 5V fSMPL = 12.
PAGE 7
LTC1286/LTC1298 U W TYPICAL PERFORMANCE CHARACTERISTICS Digital Input Logic Threshold vs Supply Voltage Minimum Clock Frequency for 0.1 LSB Error vs Temperature 200 1000 150 100 50 0 –55 –35 TA = 25°C 100 LEAKAGE CURRENT (nA) DIGITAL LOGIC THRESHOLD VOLTAGE (V) 3 VCC = VREF = 5V CLOCK FREQUENCY (kHz) Input Channel Leakage Current vs Temperature 2 5 25 45 TEMPERATURE (°C) 65 85 10 ON CHANNEL 1 OFF CHANNEL 0.
PAGE 8
LTC1286/LTC1298 W BLOCK DIAGRAM CS/SHDN CLK (DIN) VCC (VCC/ V REF) BIAS AND SHUTDOWN CIRCUIT IN + (CH0) CSAMPLE SERIAL PORT DOUT – IN – (CH1) + SAR MICROPOWER COMPARATOR CAPACITIVE DAC VREF GND PIN NAMES IN PARENTHESES REFER TO THE LTC1298 TEST CIRCUITS Load Circuit for tdDO, tr and tf Voltage Waveforms for DOUT Rise and Fall Times, tr, tf 1.
PAGE 9
LTC1286/LTC1298 TEST CIRCUITS Voltage Waveforms for tdis VIH CS Voltage Waveforms for ten LTC1286 DOUT WAVEFORM 1 (SEE NOTE 1) CS 90% 1 CLK 2 tdis DOUT WAVEFORM 2 (SEE NOTE 2) 10% B11 DOUT NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL. NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL.
PAGE 10
LTC1286/LTC1298 U W U U APPLICATION INFORMATION SERIAL INTERFACE The 2-channel LTC1298 communicates with microprocessors and other external circuitry via a synchronous, half duplex, 4-wire serial interface. The single channel LTC1286 uses a 3-wire interface (see Operating Sequence in Figures 1 and 2). Data Transfer The CLK synchronizes the data transfer with each bit being transmitted on the falling CLK edge and captured on the rising CLK edge in both transmitting and receiving systems.
PAGE 11
LTC1286/LTC1298 U W U U APPLICATION INFORMATION CS DIN 1 DIN 2 DOUT 1 DOUT 2 SHIFT MUX ADDRESS IN 1 NULL BIT SHIFT A/D CONVERSION RESULT OUT LTC1096/98 • AI01 MSB-First Data (MSBF = 0) tCYC CS tsuCS POWER DOWN CLK ODD/ SIGN START DIN DON'T CARE MSBF NULL HI-Z BIT SGL/ DIFF DOUT tSMPL B11 B10 B9 (MSB) B8 B6 B7 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11* HI-Z tDATA tCONV MSB-First Data (MSBF = 1) tCYC CS POWER DOWN tsuCS CLK ODD/ SIGN START DIN DON'T CARE SG
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LTC1286/LTC1298 U W U U APPLICATION INFORMATION Input Data Word The LTC1286 requires no DIN word. It is permanently configured to have a single differential input. The conversion result appears on the DOUT line. The data format is MSB first followed by the LSB sequence. This provides easy interface to MSB or LSB first serial ports. For MSB first data the CS signal can be taken high after B0 (see Figure 1). The LTC1298 clocks data into the DIN input on the rising edge of the clock.
PAGE 13
LTC1286/LTC1298 U W U U APPLICATION INFORMATION MSBF BIT LATCHED BY LTC1298 CS 1 2 3 4 START SGL/DIFF ODD/SIGN MSBF CLK DATA (DIN/DOUT) MPU CONTROLS DATA LINE AND SENDS MUX ADDRESS TO LTC1298 B11 B10 • • • LTC1298 CONTROLS DATA LINE AND SENDS A/D RESULT BACK TO MPU PROCESSOR MUST RELEASE DATA LINE AFTER 4TH RISING CLK AND BEFORE THE 4TH FALLING CLK LTC1298 TAKES CONTROL OF DATA LINE ON 4TH FALLING CLK LTC1286/98 F03 Figure 3.
PAGE 14
LTC1286/LTC1298 U W U U APPLICATION INFORMATION Clock Frequency 35 TA = 25°C VCC = VREF = 5V SUPPLY CURRENT (µA) 30 25 20 15 CS = 0 (AFTER CONVERSION) 10 5 1 0.002 The maximum recommended clock frequency is 200kHz for the LTC1286/LTC1298 running off a 5V supply. With the supply voltage changing, the maximum clock frequency for the devices also changes (see the typical curve of Maximum Clock Rate vs Supply Voltage).
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LTC1286/LTC1298 U W U U APPLICATION INFORMATION BOARD LAYOUT CONSIDERATIONS SAMPLE-AND-HOLD Grounding and Bypassing Both the LTC1286 and the LTC1298 provide a built-in sample-and-hold (S&H) function to acquire signals. The S&H of the LTC1286 acquires input signals from “+” input relative to “–” input during the tSMPL time (see Figure 1). However, the S&H of the LTC1298 can sample input signals in the single-ended mode or in the differential inputs during the tSMPL time (see Figure 7).
PAGE 16
LTC1286/LTC1298 U W U U APPLICATION INFORMATION Differential Inputs With differential inputs, the ADC no longer converts just a single voltage but rather the difference between two voltages. In this case, the voltage on the selected “+” input is still sampled and held and therefore may be rapidly time varying just as in single-ended mode. However, the voltage on the selected “–” input must remain constant and be free of noise and ripple throughout the conversion time.
PAGE 17
LTC1286/LTC1298 U W U U APPLICATION INFORMATION will slow the settling of the inputs. It is important that the overall RC time constants be short enough to allow the analog inputs to completely settle within the allowed time. converter, the reference input should be driven by a reference with low ROUT (ex. LT1004, LT1019 and LT1021) or a voltage source with low ROUT. RC Input Filtering It is possible to filter the inputs with an RC network as shown in Figure 9. For large values of CF (e.g.
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LTC1286/LTC1298 U W U U APPLICATION INFORMATION Noise with Reduced VREF The total input referred noise of the LTC1286 can be reduced to approximately 400µV peak-to-peak using a ground plane, good bypassing, good layout techniques and minimizing noise on the reference inputs. This noise is insignificant with a 5V reference but will become a larger fraction of an LSB as the size of the LSB is reduced. For operation with a 5V reference, the 400µV noise is only 0.33LSB peak-to-peak.
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LTC1286/LTC1298 U W U U EFFECTIVE NUMBER OF BITS (ENOBs) APPLICATION INFORMATION 12 11 74 68 10 9 62 56 8 50 7 44 6 38 5 4 3 TA = 25°C VCC = 5V fCLK = 200kHz fSMPL = 12.5kHz 2 1 0 1 10 100 INPUT FREQUENCY (kHz) 1000 LTC 1286/98 G20 Figure 12. Effective Bits and S/(N + D) vs Input Frequency Total Harmonic Distortion Total Harmonic Distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself.
PAGE 20
LTC1286/LTC1298 U TYPICAL APPLICATIONS N MICROPROCESSOR INTERFACES The LTC1286/LTC1298 can interface directly without external hardware to most popular microprocessor (MPU) synchronous serial formats (see Table 1). If an MPU without a dedicated serial port is used, then 3 or 4 of the MPU's parallel port lines can be programmed to form the serial link to the LTC1286/LTC1298. Included here is one serial interface example and one example showing a parallel port programmed to form the serial interface.
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LTC1286/LTC1298 U TYPICAL APPLICATIONS N Timing Diagram for Interface to the MC68HC11 CS CLK DIN START SGL/ DIFF ODD/ SIGN MSBF DON'T CARE DOUT MPU TRANSMIT WORD 0 0 0 0 0 0 0 SGL/ DIFF 1 ODD/ SIGN MSBF ? ? ? ? ? B10 B9 B8 X X X X X B7 X B6 B5 B4 B3 B2 B1 B0 X X X X X X X B2 B1 B0 BYTE 2 BYTE 1 MPU RECEIVED WORD B11 ? ? ? ? ? 0 ? BYTE 3 (DUMMY) B11 B10 B9 B8 B7 B6 BYTE 2 BYTE 1 B5 B3 B4 BYTE 3 LTC1286/98 AI06 Hardware and Software
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LTC1286/LTC1298 U TYPICAL APPLICATIONS N Interfacing to the Parallel Port of the INTEL 8051 Family LABEL The Intel 8051 has been chosen to demonstrate the interface between the LTC1298 and parallel port microprocessors. Normally the CS, CLK and DIN signals would be generated on 3 port lines and the DOUT signal read on a 4th port line. This works very well. However, we will demonstrate here an interface with the DIN and DOUT of the LTC1298 tied together as described in the SERIAL INTERFACE section.
PAGE 23
LTC1286/LTC1298 U TYPICAL APPLICATIONS N A “Quick Look” Circuit for the LTC1286 Users can get a quick look at the function and timing of the LT1286 by using the following simple circuit (Figure 13). VREF is tied to VCC. VIN is applied to the +IN input and the –IN input is tied to the ground. CS is driven at 1/16 the clock rate by the 74C161 and DOUT outputs the data. The output data from the DOUT pin can be viewed on an oscilloscope that is set up to trigger on the falling edge of CS (Figure 14).
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LTC1286/LTC1298 U PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. N8 Package 8-Lead Plastic DIP 0.300 – 0.320 (7.620 – 8.128) 0.045 – 0.065 (1.143 – 1.651) 0.400 (10.160) MAX 0.130 ± 0.005 (3.302 ± 0.127) 8 0.009 – 0.015 (0.229 – 0.381) ( +0.025 0.325 –0.015 8.255 +0.635 –0.381 ) 7 6 5 0.065 (1.651) TYP 0.045 ± 0.015 (1.143 ± 0.381) 0.100 ± 0.010 (2.540 ± 0.254) 0.125 (3.175) MIN 0.250 ± 0.010 (6.350 ± 0.254) 0.020 (0.508) MIN 1 2 4 3 0.018 ± 0.003 (0.