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LTC1325

Microprocessor-Controlled

Battery Management System

FEATURES

DESCRIPTION

■

Fast Charge Nickel-Cadmium, Nickel-Metal-Hydride,

Lithium Ion or Lead-Acid Batteries under

P Control

■

Flexible Current Regulation:

– Programmable 111kHz PWM Current Regulator

with Built-In PFET Driver

– PFET Current Gating for Use with External Current

Regulator or Current Limited Transformer

■

Discharge Mode

■

Measures Battery Voltage, Battery Temperature and

Ambient Temperature with Internal 10-Bit ADC

■

Battery Voltage, Temperature and Charge Time

Fault Protection

■

Built-In Voltage Regulator and Programmable

Battery Attenuator

■

Easy-to-Use 3- or 4-Wire Serial

P Interface

■

Accurate Gas Gauge Function

■

Wide Supply Range: V

= 4.5V to 16V

■

Can Charge Batteries with Voltages Greater Than V

■

Can Charge Batteries from Charging Supplies Greater

Than V

■

Digital Input Pins Are High Impedance in

Shutdown Mode

The LTC

1325 provides the core of a flexible, cost-effec-

tive solution for an integrated battery management sys-

tem. The monolithic CMOS chip controls the fast charging

of nickel-cadmium, nickel-metal-hydride, lead-acid or

lithium batteries under microprocessor control. The de-

vice features a programmable 111kHz PWM constant

current source controller with built-in FET driver, 10-bit

ADC, internal voltage regulator, discharge-before-charge

controller, programmable battery voltage attenuator and

an easy-to-use serial interface.

The chip may operate in one of five modes: power shut-

down, idle, discharge, charge or gas gauge. In power

shutdown the supply current drops to 30µA and in the idle

mode, an ADC reading may be made without any switching

noise affecting the accuracy of the measurement. In the

discharge mode, the battery is discharged by an external

transistor while the battery is being monitored by the

LTC1325 for fault conditions. The charge mode is termi-

nated by the µP while monitoring any combination of

battery voltage and temperature, ambient temperature

and charge time. The LTC1325 also monitors the battery

for fault conditions before and during charging. In the gas

gauge mode the LTC1325 allows the total charge leaving

the battery to be calculated.

■

System Integrated Battery Charger

APPLICATIONS

TYPICAL APPLICATION

, LTC and LT are registered trademarks of Linear Technology Corporation.

Battery Charger for up to 8 NiCd or NiMH Cells

1

2

3

4

5

6

7

8

9



18

17

16

15

14

13

12

11

10



PGATE

DIS

BAT



BAT



AMB



SENSE

FILTER

LTC1325

REG

OUT



CS

CLK

LTF

MCV

HTF

GND

REG



4.7µF

THERM 2

THERM 1

DIS

TRK

SENSE

LTC1325 • TA01

L1

62µH

BAT

N1

IRFZ34



4.5V TO 16V

R13



1µF

MPU

(e.g. 8051)

p1.4

p1.3

p1.2

C2

10µF

REG



22µF



0.1µF

100Ω

D1

1N6818



P1

IRF9730

Summary of content (24 pages)

PAGE 1
LTC1325 Microprocessor-Controlled Battery Management System U DESCRIPTION FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Fast Charge Nickel-Cadmium, Nickel-Metal-Hydride, Lithium Ion or Lead-Acid Batteries under µP Control Flexible Current Regulation: – Programmable 111kHz PWM Current Regulator with Built-In PFET Driver – PFET Current Gating for Use with External Current Regulator or Current Limited Transformer Discharge Mode Measures Battery Voltage, Battery Temperature and Ambient Temperature with Internal 10-
PAGE 2
LTC1325 W U PACKAGE/ORDER INFORMATION U W W W (Notes 1, 2) ORDER PART NUMBER TOP VIEW VDD to GND ............................................................. 17V All Other Pins ................................ – 0.3V to VDD + 0.3V Operating Temperature Range ..................... 0°C to 70°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec)..................
PAGE 3
LTC1325 ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER VOL Output Low Voltage VOH Output High Voltage IOZ Hi-Z Output Leakage VOHFET DIS or PGATE Output High VOLFET DIS or PGATE Output Low tdDO Delay Time, CLK↓ to DOUT Valid tdis Delay Time, CS↑ to DOUT Hi-Z ten Delay Time, CLK↓ to DOUT Enabled thDO Time DOUT Remains Valid After CLK↓ trDOUT DOUT Rise Time tfDOUT DOUT Fall Time fCLK Serial I/O Clock Frequency trPGATE PGATE Rise Time tfPGATE PGATE Fall Time fOSC Internal Oscillator Frequency A/D Converter Offset
PAGE 4
LTC1325 U W TYPICAL PERFORMANCE CHARACTERISTICS Regulator Output Voltage vs Load Current 3.082 3.076 REGULATOR OUTPUT VOLTAGE (V) VDD = 16V 3.075 VDD = 12V 3.074 VDD = 4.5V 3.073 3.072 3.071 1000 IREG = 0 3.081 900 3.080 VDD = 16V 3.079 VDD = 12V 3.078 3.077 VDD = 4.5V 3.076 3.075 3.074 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 LOAD CURRENT (mA) 4.
PAGE 5
LTC1325 U W TYPICAL PERFORMANCE CHARACTERISTICS PGATE Fall Time vs Load Capacitance PGATE Rise Time vs Load Capacitance Differential Nonlinearity 1000 1200 1.0 PGATE FALL TIME (ns) PGATE RISE TIME (ns) 800 TA = 27°C 800 TA = 70°C 600 TA = 0°C 400 DIFFERENTIAL NONLINEARITY (LSB) 900 1000 TA = 27°C 700 600 TA = 70°C 500 400 TA = 0°C 300 200 200 100 0 0 0 2 4 6 8 10 12 14 16 18 20 LOAD CAPACITANCE (nF) 0 2 4 0 –0.5 Integral Nonlinearity RISE TIME 10 8 6 FALL TIME 4 2 1.
PAGE 6
LTC1325 U U U PIN FUNCTIONS REG (Pin 1): Internal Regulator Output. The regulator provides a steady 3.072V to the internal analog circuitry and provides a temperature stable reference voltage for generating MCV, HTF, LTF and thermistor bias voltages with external resistors. Requires a 4.7µF or greater bypass capacitor to ground. DOUT (Pin 2): TTL Data Output Signal for the Serial Interface. DOUT and DIN may be tied together to form a 3-wire interface, or remain separated to form a 4-wire interface.
PAGE 7
LTC1325 W BLOCK DIAGRAM VDD 18 DIGITAL INPUT CIRCUITS 5V DIGITAL REGULATOR GND 3.
PAGE 8
LTC1325 TEST CIRCUITS Voltage Waveforms for DOUT Delay Time, tdDO Voltage Waveforms for DOUT Rise and Fall Times, tr, tf 2.4V CLK 0.8V 0.4V tdDO tr 2.4V tf LTC1325 • TC04 DOUT 0.4V LTC1325 • TC03 On and Off Channel Leakage Voltage Waveforms for tdis 3.
PAGE 9
LTC1325 WU W TI I G DIAGRA MSB-FIRST DATA (MSBF = 1) CS CLK START MSBF DIN DOUT NULL D9 HI-Z BATP D1 D0 ADC DATA COMMAND WORD FS HI-Z STATUS WORD MSB-FIRST DATA (MSBF = 0) CS CLK VR1 START DIN DOUT NULL D9 HI-Z D1 D0 D1 ADC DATA COMMAND WORD BATP D9 FS STATUS WORD HI-Z LTC1325 • TD NOTE: THE TIMING DIAGRAM SHOWS TWO POSSIBLE COMMAND WORDS.
PAGE 10
LTC1325 U U U FUNCTIONAL DESCRIPTIO COMMAND WORD Bit 5: MSB-First/LSB-First (MSBF) The command word is 22 bits long and contains all the information needed to configure and control the chip. On power-up all bits are cleared to logical “0.” The ADC data is programmed for MSB-first or LSB-first sequence using the MSBF bit. See Serial I/O description for details.
PAGE 11
LTC1325 U U U FUNCTIONAL DESCRIPTIO Bit 13: Power Shutdown (PS) PS selects between the normal operating mode, or the shutdown mode. PS 0 1 DESCRIPTION Normal Operation Shutdown All Circuits Except Digital Inputs Bits 14 to 16: Duty Ratio Select (DR0 to DR2) DR2, DR1 and DR0 select the duty cycle of the charging loop operation (not 111kHz PWM duty cycle). The last three selections place the chip into a test mode and should not be used.
PAGE 12
LTC1325 U U U FUNCTIONAL DESCRIPTIO Bit 3: Maximum Cell Voltage (FMCV) The MCV bit indicates when the battery cell voltage has exceeded the preset limit. The bit is set when VCELL is greater than the voltage at the MCV pin. FMCV 0 1 CONDITIONS VCELL < VMCV VCELL > VMCV Bit 4: End Discharge Voltage (FEDV) The EDV bit indicates when the battery cell voltage has dropped below an internally preset limit.
PAGE 13
LTC1325 U U U FUNCTIONAL DESCRIPTIO (MCV), minimum cell voltage exceeded (EDV), high temperature limit exceeded (HTF), low temperature limit exceeded (LTF) and time limit exceeded (tOUT). When a fault condition occurs, the discharge and charge loops are disabled or prevented from turning on and the fail-safe bit (FS) is set. The chip is reset by shifting in a new command word with the fail-safe clear FSCLR bit set. The 8-bit status word contains the state of each fault condition.
PAGE 14
LTC1325 U U U FUNCTIONAL DESCRIPTIO VDD 4.5V TO 16V CHARGE PGATE DR0 TO DR2 3 DUTY RATIO GENERATOR D1 1N5818 L1 RDIS GG ONE SHOT S1 S + R RTRK DIS DISCHARGE 111kHz OSCILLATOR Q P1 IRF9Z30 C1 16pF R1 500k R2 125k S2 RF 1k S4 BATTERY N1 IRFZ34 SENSE CF FILTER RSENSE S3 A2 – – TO ADC MUX REG 3.072V A1 + GG VR1 VR0 DAC VOLTAGE 0 0 0 18mV 0 0 1 34mV 0 1 0 55mV 0 1 1 160mV 1 X X 0mV VDAC DAC 2 VR0, VR1 GG CHIP (GAS GAUGE) BOUNDARY LTC1325 • F04 Figure 4.
PAGE 15
LTC1325 U U U FUNCTIONAL DESCRIPTIO Gas Gauge Mode Command: MOD1 = 1, MOD0 = 1, PS = 0 Status: BATP = X, BATR = X, FMCV = X, FEDV = X, FHTF = X, FLTF = X, t OUT = X In the gas gauge mode, the average voltage across the sense resistor can be measured to determine the average battery load current. The output of the DAC is set to ground and switches S1, S3 and S4 are closed. A1 is configured as an inverting amplifier with R1 and R2 setting the gain to – 4.
PAGE 16
LTC1325 U U U FUNCTIONAL DESCRIPTIO communicate with the microprocessor. Data is transmitted in both directions on a single wire. The processor pin connected to this data line should be configurable as either an input or an output. The LTC1325 will take control of the data line and drive it low after the 23rd falling CLK edge after the start bit is received. Therefore the processor port must be switched to an input before this happens to avoid a conflict.
PAGE 17
LTC1325 U W U U APPLICATIONS INFORMATION (3). Alternatively, β may be calculated from the RT/RTO ratio using equation (4) or from α, using equation (6). As a numerical example, consider the Panasonic ERT-D2FHL103S thermistor which has the following characteristics: 1. RT (25°C) = RTO = 10k 2. α = – 4.6%/°C at TO = 25°C 3. Ratio R25/R50 = 2.9 Using equation (4) and R25/R50 = 2.9, β = (323 × 298)In (2.9)/(298 – 323) = 4099k. Alternatively, using equation (6) and α = – 4.6%/°C, β = – (– 0.
PAGE 18
LTC1325 U W U U APPLICATIONS INFORMATION The LTC1325 has five duty ratio and four VDAC settings giving 20 possible charge rates (for a given value of RSENSE) as shown in the following table.
PAGE 19
LTC1325 U W U U APPLICATIONS INFORMATION where, IF = forward diode current, IF′ = forward diode current just prior to turn off, VF = forward drop, VR = reverse diode voltage (approximately equal to VDD), f = PWM frequency (111kHz), and tRR = reverse recovery time The power and maximum reverse voltage ratings of the diode should be greater than PdD1 and VDD respectively. The catch diode should also have fast turn-on times to reduce the voltage glitch at its cathode when turning on.
PAGE 20
LTC1325 U W U U APPLICATIONS INFORMATION 8. REG Pin Loading: The 3.072V regulator has a load regulation specification of – 5mV/mA. Since the ADC uses the same regulator as reference, it is desirable to reduce loading effects on the REG pin especially over temperature. Thermistors with RTO values of at least 10k at 25°C are recommended. At 50°C, the thermistor resistance could drop by a factor of 3 from its value at 25°C. RL is chosen as explained in the section on Temperature Sensing.
PAGE 21
LTC1325 U U W U APPLICATIONS INFORMATION 3. The MSBF bit is set depending on whether the microprocessor clocks in serial data with MSB- or LSB-first. 4. The DS0 to DS2 bits can be anything except when entering idle mode or when requesting for ADC readings. In these cases, DS0 to DS2 are set to select the desired reading: TBAT, VCELL or TAMB. 5. The PS bit should always be 0 so that the LTC1325 does not go into shutdown mode. 6. The DR0 to DR2 should not select any of the test modes.
PAGE 22
LTC1325 U W U U APPLICATIONS INFORMATION idle mode to minimize noise. The microprocessor should either disregard readings or wait for a second or so before taking a reading. This is to allow VCELL to decay to the correct cell voltage. The worst case time constant is 150kΩ(CF ). 10. Prior to the first START command, the battery divider setting may be incorrect so that CF may charge to a voltage that causes EDV, BATR or MCV faults. The worst case time constant is as in (9).
PAGE 23
LTC1325 U U W U APPLICATIONS INFORMATION LABEL MNEMONIC OPERAND CSLOW LOOP1 LOOP2 LOOP3 LDAA STAA LDAA STAA LDX BCLR LDAA STAA TST BPL LDAA STAA TST BPL LDAA STAA TST BPL LDAA STAA #$51 $1028 #$39 $1009 #$1000 $08,X,#$01 #$02 $102A $1029 LOOP1 #$24 $102A $1029 LOOP2 #$03 $102A $1029 LOOP3 #$C0 $102A COMMENTS LABEL MNEMONIC OPERAND COMMENTS Write control byte to the SPCR LOOP4 TST BPL LDAA ANDA STAA LDAA STAA LOOP5 TST BPL LDAA STAA LDAA STAA LOOP6 TST BPL LDAA STAA BSET BRA Check for SPI tr
PAGE 24
LTC1325 U PACKAGE DESCRIPTION Dimension in inches (millimeters) unless otherwise noted. N Package 18-Lead Plastic DIP 0.130 ± 0.005 (3.302 ± 0.127) 0.300 – 0.325 (7.620 – 8.255) 0.015 (0.381) MIN 0.009 – 0.015 (0.229 – 0.381) +0.025 0.325 –0.015 ( ) 18 17 16 15 14 13 12 11 10 1 2 3 4 5 6 7 8 9 0.065 0.255 ± 0.015* (1.651) (6.477 ± 0.381) TYP 0.005 (0.127) MIN 0.100 ± 0.010 (2.540 ± 0.254) *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.