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LTC1343

Software-Selectable

Multiprotocol Transceiver

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Software-Selectable Transceiver Supports:

RS232, RS449, EIA-530, EIA-530-A, V.35, V.36,

X.21

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NET1 and NET2 Compliant

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Software-Selectable Cable Termination Using

the LTC1344

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4-Driver/4-Receiver Configuration Provides a

Complete 2-Chip DTE or DCE Port

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Operates from Single 5V Supply

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Internal Echoed Clock and Loop-Back Logic

The LTC

1343 is a 4-driver/4-receiver multiprotocol trans-

ceiver that operates from a single 5V supply. Two LTC1343s

form the core of a complete software-selectable DTE or DCE

interface port that supports the RS232, RS449, EIA-530,

EIA-530-A, V.35, V.36 or X.21 protocols. Cable termination

may be implemented using the LTC1344 software-selectable

cable termination chip or by using existing discrete designs.

The LTC1343 runs from a single 5V supply using an internal

charge pump that requires only five space saving surface mount

capacitors. The mode pins are latched internally to allow sharing

of the select lines between multiple interface ports.

Software-selectable echoed clock and loop-back modes help

eliminate the need for external glue logic between the serial

controller and line transceiver. The part features a flow-

through architecture to simplify EMI shielding and is available

in the 44-lead SSOP surface mount package.

DTE Multiprotocol Serial Interface with DB-25 Connector

, LTC and LT are registered trademarks of Linear Technology Corporation.

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Data Networking

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CSU and DSU

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Data Routers

LTC1343

RTSDTRDSR DCDCTS RL

D3D4

LTC1343

TXDSCTETXCRXCRXDTM

LL A (141)

TXD A (103)

TXD B

SCTE A (113)

SCTE B

RXC A (115)

RXC B

RXD A (104)

RXD B

RTS A (105)

RTS B

DTR A (108)

DTR B

CTS A (106)

CTS B

TM A (142)

SGND (102)

SHIELD (101)

21424111512179314192023622 810513 21 7 1625

1343 TA01

DB-25 CONNECTOR

LTC1344

D3D4

TXC A (114)

TXC B

RL A (140)

DCD A (109)

DCD B

DSR A (107)

DSR B

FEATURES

DESCRIPTIO

APPLICATIO S

TYPICAL APPLICATIO

Summary of content (28 pages)

PAGE 1
LTC1343 Software-Selectable Multiprotocol Transceiver U FEATURES ■ ■ ■ ■ ■ ■ DESCRIPTIO The LTC®1343 is a 4-driver/4-receiver multiprotocol transceiver that operates from a single 5V supply. Two LTC1343s form the core of a complete software-selectable DTE or DCE interface port that supports the RS232, RS449, EIA-530, EIA-530-A, V.35, V.36 or X.21 protocols. Cable termination may be implemented using the LTC1344 software-selectable cable termination chip or by using existing discrete designs.
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LTC1343 U W U U W W W ABSOLUTE MAXIMUM RATINGS PACKAGE/ORDER INFORMATION (Note 1) Supply Voltage ....................................................... 6.5V Input Voltage Transmitters ........................... – 0.3V to (VCC + 0.3V) Receivers ............................................... – 18V to 18V Logic Pins .............................. – 0.3V to (VCC + 0.3V) Output Voltage Transmitters ................. (VEE – 0.3V) to (VDD + 0.3V) Receivers ................................ – 0.
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LTC1343 ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V (Notes 2, 3) SYMBOL PARAMETER CONDITIONS tr Supply Rise Time No-Cable Mode or Power-Up to Turn On MIN TYP MAX 2 UNITS ms Logic Inputs and Outputs VIH Logic Input High Voltage ● 2 VIL Logic Input Low Voltage ● 0.
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LTC1343 ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
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LTC1343 ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V (Notes 2, 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 0.2 0.3 V V V.10 Receiver VTH Receiver Input Threshold Voltage ∆VTH Receiver Input Hysteresis IIN Receiver Input Current RIN t r, t f 0°C ≤ TA ≤ 70°C –7V ≤ VCM ≤ 7V, – 40°C ≤ TA ≤ 85°C ● ● – 0.2 – 0.3 11 ● 50 mV ±0.
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LTC1343 U U U PIN FUNCTIONS VCC (Pin 8): Positive Supply for the Transceivers. 4.75V ≤ VCC ≤ 5.25V. Tie to PWRVCC (Pin 3). respective input buffers. The data latch allows the logic lines to be shared between multiple I/O ports. D4 (Pin 9): TTL Level Driver 4 Input. LB (Pin 23): TTL Level Loop-Back Select Input. When low the chip enters the loop-back configuration and is configured for normal operation when LB is high. The data on LB is latched when LATCH is high.
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LTC1343 TEST CIRCUITS A RL 50Ω B RL 100Ω A VOD RL 50Ω CL 100pF B CL 100pF A R 15pF VOC B 1343 F01 1343 F02 Figure 1. RS422 Driver Test Circuit Figure 2. RS422 Driver/Receiver AC Test Circuit 50Ω B D 125Ω VCM 50Ω B 125Ω R VOD A A 15pF 50Ω 50Ω 1343 F03 Figure 3. V.35 Driver/Receiver Test Circuit D A D A A R RL CL 15pF 1343 F04 1343 F04 Figure 4. V.10/V.28 Driver Test Circuit Figure 5. V.10/V.
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LTC1343 U W W SWITCHI G TI E WAVEFOR S 5V f = 1MHz : t r ≤ 10ns : t f ≤ 10ns 1.5V D 0V 1.5V t PHL t PLH B–A VO 90% 50% –VO 10% tr 90% VDIFF = V(A) – V(B) 50% 1/2 VO 10% tf A VO B t SKEW t SKEW 1343 F06 Figure 6. V.11, V.35 Driver Propagation Delays VOD2 B–A –VOD2 f = 1MHz : t r ≤ 10ns : t f ≤ 10ns 0V INPUT t PLH VOH R VOL 0V t PHL OUTPUT 1.5V 1.5V 1343 F07 Figure 7. V.11, V.35 Receiver Propagation Delays 3V 1.5V 1.
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LTC1343 U U W U APPLICATIONS INFORMATION Overview software-selectable cable termination chip or by using existing discrete designs. The LTC1343 is a 4-driver/4-receiver multiprotocol transceiver that operates from a single 5V supply. Two LTC1343s form the core of a complete software-selectable DTE or DCE interface port that supports the RS232, RS449, EIA-530, EIA-530-A, V.35, V.36 or X.21 protocols.
PAGE 10
LTC1343 U U W U APPLICATIONS INFORMATION will configure the port for DCE mode when high, and DTE when low. RL (Remote Loop-back) and RI (Ring Indicate). The LTC1344 cable termination chip is used only for the clock and data signals because they must support V.35 cable termination. The control signals do not need any external resistors. The interface protocol may be selected simply by plugging the appropriate interface cable into the connector.
PAGE 11
LTC1343 U W U U APPLICATIONS INFORMATION remain off even though the signal voltage is beyond the supply voltage for the FET drivers or the power is off. PORT #1 M1 M2 DCE/DTE CONNECTOR #1 M0 LATCH PORT #2 V.10 (RS423) Interface M2 DCE/DTE CONTROLLER CONNECTOR #2 M0 M1 LATCH M0 M1 M1 M2 M2 DCE/DTE DCE/DTE LATCH 1 CONNECTOR #3 PORT #3 M0 Using the LTC1344 along with the LTC1343 solves the cable termination switching problem.
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LTC1343 U U W U APPLICATIONS INFORMATION The V.10 receiver configuration in the LTC1343 and LTC1344 is shown in Figure 15. In V.10 mode switches S1 and S2 inside the LTC1344 and S3 inside the LTC1343 are turned off. Switch S4 inside the LTC1343 shorts the noninverting receiver input to ground so the B input at the connector can be left floating. The cable termination is then the 30k input impedance to ground of the LTC1343 V.10 receiver. V.11 (RS422) Interface A typical V.
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LTC1343 U U W U APPLICATIONS INFORMATION A' A' A R1 51.5Ω S1 S2 LTC1344 R8 6k R2 51.5Ω R5 20k R1 51.5Ω R6 10k S3 R3 124Ω A LTC1343 B' R7 10k R4 20k B B' GND 1343 F19 Figure 19. V.28 Receiver Configuration A typical V.35 balanced interface is shown in Figure 20. A V.35 differential generator with outputs A and B with ground C is connected to a differential receiver with ground C', inputs A' connected to A, B' connected to B. The V.
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LTC1343 U U W U APPLICATIONS INFORMATION Echoed Clock Mode Loop-Back The LTC1343 contains the logic to generate the echoed clock when using a serial controller with only two clock pins. Figure 23 shows the chip in both the DTE and DCE echoed clock in EIA-530 mode. The control signals are not shown. The echoed clock configuration is selected by pulling the EC pin low. On the DTE side the transmit clock TXC receiver output is connected to the echoed clock, SCTE, driver input.
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LTC1343 U U W U APPLICATIONS INFORMATION SERIAL CONTROLLER LL LTC1343 LTC1344 D1 LTC1344 LL LL LTC1343 R4 SERIAL CONTROLLER LL TXD D2 TXD TXD 103Ω R3 TXD SCTE D3 SCTE SCTE 103Ω R2 SCTE D4 R1 RXD D2 RXD TM R4 TM TM D1 TM LATCH RXD EC 103Ω LB R3 DCE/DTE RXD CTRL/CLK RXC M2 D3 M1 RXC M0 RXC M0 M1 M2 DCE/DTE LATCH 103Ω M0 M1 M2 DCE/DTE LATCH R2 LATCH RXC EC TXC LB D4 DCE/DTE TXC CTRL/CLK TXC M2 103Ω M1 R1 M0 TXC 1 0 1 0 0 0 1 0 1 0
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LTC1343 U U W U APPLICATIONS INFORMATION SERIAL CONTROLLER LL LTC1343 LTC1344 D1 LTC1344 LL LL LTC1343 R4 SERIAL CONTROLLER LL TXD D2 TXD TXD 103Ω R3 RXD TXC D3 TXCE SCTE 103Ω R2 RXC D4 R1 TXD TM R4 TM TM D1 TM LATCH D2 EC RXD LB RXD DCE/DTE 103Ω CTRL/CLK R3 M2 RXD M1 TXC M0 D3 M0 M1 M2 DCE/DTE LATCH RXC M0 M1 M2 DCE/DTE LATCH RXC LATCH 103Ω EC R2 LB RXC DCE/DTE D4 CTRL/CLK TXC M2 TXC M1 103Ω M0 R1 1 0 1 0 0 0 0 0 1 0 1 0 0 1 0
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LTC1343 U W U U APPLICATIONS INFORMATION The no-cable mode (M0 = M1 = M2 = 1) is intended for the case when the cable is disconnected from the connector. The charge pump, bias circuitry, drivers and receivers are turned off, the driver outputs are forced into a high impedance state, and the supply current drops to less than 200µA. It can also be used to share I/O lines with other drivers and receivers without loading down the signals.
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LTC1343 U W U U APPLICATIONS INFORMATION The EC pin has no affect on the configuration when CTRL/ CLK is high except to allow the DCE/DTE pin to become an enable. When DCE/DTE is low, the driver 1 output is enabled. The receiver 4 output goes into three-state and the input presents a 30kΩ load to ground. drivers and receivers into a high impedance state. In the DCE mode, the middle two LTC1343s are enabled and the top and bottom LTC1343s disabled.
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LTC1343 U U W U APPLICATIONS INFORMATION C6 100pF C7 100pF 3 C8 100pF 8 11 12 13 LTC1344 VCC 5V 14 + C1 1µF 2 43 42 4 CHARGE PUMP 3 + C5 1µF 41 8 6 TXD D4 10 12 13 TXC R1 14 RXC R2 15 RXD R3 16 R4 20 CTRL 22 LATCH 11 INVERT 25 423 SET TM R1 100k + VCC C11 1µF C9 1µF + C12 1µF CHARGE PUMP 14 15 CTS 16 VCC LATCH R2 100k LB 18 17 19 20 22 23 24 1 18 LL A (141) 2 TXD A (103) 14 TXD B 24 SCTE A (113) 11 SCTE B TXC A (114) TXC B RXC A (115) RXC B RXD A (104) RXD
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LTC1343 U U W U APPLICATIONS INFORMATION C6 100pF C7 100pF 3 C8 100pF 8 11 12 13 LTC1344 VCC 5V 14 C1 1µF + 2 43 42 4 CHARGE PUMP 3 + C5 1µF 41 8 6 RXD D2 7 RXC D3 9 TXC D4 10 12 13 VCC R2 15 TXD LL R1 100k + VCC C11 1µF C9 1µF + 27 44 2 43 42 3 + C12 1µF 41 8 6 7 DSR 9 DCD 10 12 13 VCC VCC LATCH R2 100k LB D2 D3 16 15 18 17 19 20 22 23 24 1 RXD A (104) RXD B RXC A (115) RXC B TXC A (114) TXC B 24 SCTE A (113) 11 SCTE B 2 TXD A (103) 14 TXD B 18
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LTC1343 U U W U APPLICATIONS INFORMATION C6 100pF C7 100pF 3 C8 100pF 8 11 12 13 LTC1344 VCC 5V 14 + C1 1µF 2 43 42 4 CHARGE PUMP 3 + C5 1µF 41 8 6 DTE_TXD/DCE_RXD D2 7 DTE_SCTE/DEC_RXC D3 9 D4 10 12 13 DTE_TXC/DCE_TXC R1 14 DTE_RXC/DCE_SCTE R2 15 DTE_RXD/DCE_TXD DTE_TM/DCE_LL R1 100k + C11 1µF C9 + 1µF VCC C12 1µF 43 42 41 7 DTE_DTR/DCE_DSR 9 10 12 13 DTE_DCD/DCE_DCD D2 D3 D4 R3 28 27 R4 20 CTRL 22 LATCH 11 INVERT 25 423 SET 21 DCE 19 M2 18 M1 17 M0 R1
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LTC1343 U U W U APPLICATIONS INFORMATION LTC1343 5 D1 6 D2 7 21 DCE 9 D3 D4 10 12 39 38 37 36 35 34 33 C6 100pF C7 100pF 3 8 C8 100pF 11 12 13 LTC1344 13 R2 32 31 30 29 R3 28 27 R1 14 15 DCE/ DTE 5 16 R4 4 6 7 9 10 16 15 18 17 19 20 22 26 DCE/DTE DB-25 CONNECTOR LTC1343 5 TM D1 6 RXD D2 7 21 DCE 9 RXC TXC VCC D3 D4 10 12 13 15 TXD 16 LL 25 38 37 36 35 34 33 3 16 17 9 15 12 R2 32 31 30 29 R3 28 27 R1 14 SCTE 39 R4 26 7 CTS DSR VCC DCD DTR R
PAGE 23
LTC1343 U U W U APPLICATIONS INFORMATION C6 100pF C7 100pF 3 C8 100pF 8 11 12 13 LTC1344 VCC 5V 14 C1 1µF + 2 43 42 4 CHARGE PUMP 3 + C5 1µF 41 8 TXD D4 10 12 13 TXC R1 14 RXC R2 15 RXD TM R1 100k + C11 1µF C9 1µF VCC + R3 16 R4 20 CTRL 22 LATCH 11 INVERT 25 423 SET C12 1µF LATCH R2 100k LB 18 17 19 20 22 23 24 1 18 LL A (141) 2 TXD A (103) 14 TXD B 24 SCTE A (113) 11 SCTE B 12 17 9 3 16 TXC A (114) TXC B RXC A (115) RXC B RXD A (104) RXD B TM A (142) VCC 7
PAGE 24
LTC1343 U U W U APPLICATIONS INFORMATION C6 100pF C7 100pF 3 C8 100pF 8 11 12 13 LTC1344 VCC 5V 14 C1 1µF + 2 43 42 4 CHARGE PUMP 3 + C5 1µF 6 RXD D2 7 RXC D3 9 TXC D4 10 12 13 VCC LL R1 100k + C11 1µF + C9 1µF VCC C12 1µF 44 2 43 42 4 CHARGE PUMP 41 8 6 CTS 7 DSR 9 DCD VCC 10 12 13 D2 D3 D4 R3 28 27 R4 20 CTRL 22 LATCH 11 INVERT 25 423 SET 21 DCE 19 M2 18 M1 17 M0 R1 16 RL VCC LATCH R2 100k 10 16 15 18 17 19 20 22 23 24 1 RXD A (104) RXD B RX
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LTC1343 U U W U APPLICATIONS INFORMATION C6 100pF C7 100pF 3 C8 100pF 8 12 13 11 LTC1344 VCC 5V 14 + C1 1µF 2 43 42 4 CHARGE PUMP 3 + C5 1µF 41 8 D4 10 12 13 R2 15 DTE_RXD/DCE_TXD R1 100k + C11 1µF C9 1µF VCC + R3 27 16 R4 20 CTRL 22 LATCH 11 INVERT 25 423 SET 26 21 DCE 19 M2 18 M1 17 M0 40 GND 23 LB C12 1µF 44 43 42 CHARGE PUMP 41 8 DTE 2 TXD A 14 TXD B 24 SCTE A 11 SCTE B 15 12 17 9 3 16 TXC A TXC B RXC A RXC B RXD A RXD B 7 1 TXC A TXC B SCTE A SCTE B TXD
PAGE 26
LTC1343 U U W U APPLICATIONS INFORMATION C6 100pF C7 100pF 3 C8 100pF 8 11 12 13 LTC1344 VCC 5V 14 C1 1µF + 2 43 42 4 CHARGE PUMP 3 + C5 1µF 41 8 6 DTE_TXD/DCE_RXD D2 7 DTE_SCTE/DEC_RXC D3 9 D4 10 12 13 DTE_TXC/DCE_TXC R1 14 DTE_RXC/DCE_SCTE R2 15 DTE_RXD/DCE_TXD DTE_TM/DCE_LL R1 100k + C11 1µF + C9 1µF VCC C12 1µF 43 42 41 7 DTE_DTR/DCE_DSR 9 10 12 13 DTE_DCD/DCE_DCD VCC LATCH R2 100k LB D2 D3 D4 R3 28 27 R4 20 CTRL 22 LATCH 11 INVERT 25 423 SET 26 2
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LTC1343 U U W U APPLICATIONS INFORMATION C6 100pF C7 100pF 3 C8 100pF 8 12 13 11 LTC1344 VCC 5V 14 C1 1µF + 44 2 43 42 4 CHARGE PUMP 3 + C5 1µF 41 8 DTE_TXD/DCE_RXD D4 10 12 13 DTE_TXC/DCE_TXC R3 32 31 30 29 28 27 16 R4 20 CTRL 22 LATCH 11 INVERT 25 423 SET 26 21 DCE 19 M2 18 M1 17 M0 R1 14 DTE_RXC/DCE_SCTE R2 15 DTE_RXD/DCE_TXD R1 100k + C11 1µF C9 1µF VCC + 40 GND 23 LB C12 1µF 44 43 42 CHARGE PUMP 41 8 LB DTE 2 TXD A 14 TXD B 24 SCTE A 11 SCTE B 15 12
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LTC1343 U PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. GW Package 44-Lead Plastic SSOP (Wide 0.300) (LTC DWG # 05-08-1642) 17.805 – 18.059* (0.701 – 0.711) 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 10.160 – 10.414 (0.400 – 0.410) 7.417 – 7.595** (0.292 – 0.299) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 2.286 – 2.387 (0.090 – 0.094) 2.463 – 2.641 (0.097 – 0.104) 0.254 – 0.406 × 45° (0.010 – 0.016) 0° – 8° TYP 0.231 – 0.3175 (0.