Figure 12: Mode Selection by the Controller
has a unique data latch signal which acts as a write enable.
When the LATCH pin is low the buffers on the M0, M1, M2,
CTRL/CLK, DCE/DTE, LB and EC pins are transparent.
When the LATCH pin is pulled high the buffers latch the
data and changes on the input pins will no longer affect
The mode selection may also be accomplished by using
jumpers to connect the mode pins to ground or V
Traditional implementations have included switching re-
sistors with expensive relays, or requiring the user to
change termination modules every time the interface
standard has changed. Custom cables have been used
with the termination in the cable head, or separate termi-
nations are built on the board and a custom cable routes
the signals to the appropriate termination. Switching the
terminations with FETs is difficult because the FETs must
remain off even though the signal voltage is beyond the
supply voltage for the FET drivers or the power is off.
Using the LTC1344 along with the LTC1343 solves the
cable termination switching problem. Via software con-
trol, the LTC1344 provides termination for the V.10
(RS423), V.11 (RS422), V.28 (RS232) and V.35 electrical
V.10 (RS423) Interface
A typical V.10 unbalanced interface is shown in Figure 13.
A V.10 single-ended generator output A with ground C is
connected to a differential receiver with inputs A' con-
nected to A, and input B' connected to the signal return
ground C. The receiver’s ground C' is separate from the
signal return. Usually, no cable termination is required for
V.10 interfaces, but the receiver inputs must be compliant
with the impedance curve shown in Figure 14.
Figure 14. V.10 Receiver Input Impedance
Figure 13. Typical V.10 Interface
CONNECTOR #1CONNECTOR #2CONNECTOR #3