Datasheet

14
LTC1343
APPLICATIONS INFORMATION
WUU
U
Echoed Clock Mode
The LTC1343 contains the logic to generate the echoed
clock when using a serial controller with only two clock
pins. Figure 23 shows the chip in both the DTE and DCE
echoed clock in EIA-530 mode. The control signals are not
shown. The echoed clock configuration is selected by
pulling the EC pin low. On the DTE side the transmit clock
TXC receiver output is connected to the echoed clock,
SCTE, driver input. The TXC pin on the serial controller is
configured as an input. On the DCE side, the transmit clock
from the serial controller is used to generate both TXC and
RXC. A phase inverter is placed in the TXC signal path on
both the DTE and DCE side to help correct phase problems
with long cables. If the Invert pin is high, the phase of the
data is inverted.
Loop-Back
The LTC1343 contains logic for placing the interface into
a loop-back configuration for testing. Both DTE and DCE
loop-back configurations are supported. Figure 24 shows
a complete DTE interface in the loop-back configuration
with the EC pin pulled high. The loop-back configuration is
selected by pulling the LB pin low. Both the line side and
logic side signals are looped back. The DCE loop-back
configuration is shown in Figure 25.
If the echoed clock mode is selected by pulling EC low, D3
becomes an output and is connected to receiver 2’s output
R3 in DTE mode as shown in Figure 26. In the echoed clock
DCE loop-back mode, driver 4 is connected to driver 3’s
input D3 as shown in Figure 27.
Figure 23. EIA-530 Echoed Clock Configuration
LTC1343
DCEDTE
LTC1343LTC1344
LTC1344
1343 F23
D1
D4
D4
D3
D2
R1
R4
103
103
103
103
103
R3
LL
TXD
TXC
INVERT
RXC
RXD
TM
SERIAL
CONTROLLER
R3
R2
R1
R4
D3
D2
D1
LL
RXD
RXC
INVERT
TXC
TXD
TM
SERIAL
CONTROLLER
R2
M0
M1
M2
CTRL/CLK
DCE/DTE
LB
EC
LATCH
M0
M1
M2
DCE/DTE
LATCH
1 0 1 0 0 1 0 0
M0
M1
M2
CTRL/CLK
DCE/DTE
LB
EC
LATCH
1 0 1 0 1 1 0 01 0 1 0 0
M0
M1
M2
DCE/DTE
LATCH
1 0 1 1 0
LL
TXD
SCTE
TXC
RXC
RXD
TM