Datasheet

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LTC1403-1/LTC1403A-1

14031fc

BLOCK DIAGRAM

FEATURES DESCRIPTION

Serial 12-Bit/14-Bit, 2.8Msps

Sampling ADCs with Shutdown

APPLICATIONS

2.8Msps Conversion Rate

Low Power Dissipation: 14mW

3V Single Supply Operation

2.5V Internal Bandgap Reference can be Overdriven

3-Wire Serial Interface

Sleep (10µW) Shutdown Mode

Nap (3mW) Shutdown Mode

80dB Common Mode Rejection

±1.25V Bipolar Input Range

Tiny 10-Lead MSE Package

Communications

Data Acquisition Systems

Uninterrupted Power Supplies

Multiphase Motor Control

Multiplexed Data Acquisition

The LTC

1403-1/LTC1403A-1 are 12-bit/14-bit, 2.8Msps

serial ADCs with differential inputs. The devices draw only

4.7mA from a single 3V supply and come in a tiny 10-lead

MSE package. A Sleep shutdown feature lowers power

consumption to 10µW. The combination of speed, low

power and tiny package makes the LTC1403-1/LTC1403A-1

suitable for high speed, portable applications.

The 80dB common mode rejection allows users to elimi-

nate ground loops and common mode noise by measuring

signals differentially from the source.

The devices convert –1.25V to 1.25V bipolar inputs

differentially. The absolute voltage swing for A

and

–

extends from ground to the supply voltage.

The serial interface sends out the conversion results during

the 16 clock cycles following CONV

↑

for compatibility with

standard serial interfaces. If two additional clock cycles

for acquisition time are allowed after the data stream in

between conversions, the full sampling rate of 2.8Msps

can be achieved with a 50.4MHz clock.

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the property

of their respective owners.

14031 TA01a

–

S & H

GND

EXPOSED PAD

LTC1403A-1

REF

10µF

–

14-BIT ADC

3V10µF

14-BIT LATCH

THREE-

STATE

SERIAL

OUTPUT

PORT

2.5V

REFERENCE

TIMING

LOGIC

SDO

CONV

SCK

5 6 11

THD, 2nd and 3rd vs Input

Frequency for Differential Input

Signals

FREQUENCY (MHz)

0.1

–80

THD, 2nd, 3rd (dB)

–74

–68

–62

–56

1 10 100

14031 TA01b

–86

–92

–98

–104

–50

–44

THD

3rd

2nd

Summary of content (22 pages)

PAGE 1
LTC1403-1/LTC1403A-1 Serial 12-Bit/14-Bit, 2.8Msps Sampling ADCs with Shutdown FEATURES n n n n n n n n n n DESCRIPTION The LTC®1403-1/LTC1403A-1 are 12-bit/14-bit, 2.8Msps serial ADCs with differential inputs. The devices draw only 4.7mA from a single 3V supply and come in a tiny 10-lead MSE package. A Sleep shutdown feature lowers power consumption to 10µW. The combination of speed, low power and tiny package makes the LTC1403-1/LTC1403A‑1 suitable for high speed, portable applications. 2.
PAGE 2
LTC1403-1/LTC1403A-1 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Notes 1, 2) Supply Voltage (VDD) ..................................................4V Analog Input Voltage (Note 3) ....................................–0.3V to (VDD + 0.3V) Digital Input Voltage .................. – 0.3V to (VDD + 0.3V) Digital Output Voltage ...................– 0.3V to (VDD + 0.3V) Power Dissipation................................................100mW Operation Temperature Range LTC1403C-1/LTC1403AC-1....................
PAGE 3
LTC1403-1/LTC1403A-1 ANALOG INPUT The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 3V SYMBOL PARAMETER CONDITIONS tACQ Sample-and-Hold Acquisition Time tAP Sample-and-Hold Aperture Delay Time tJITTER Sample-and-Hold Aperture Delay Time Jitter CMRR Analog Input Common Mode Rejection Ratio MIN (Note 6) TYP MAX UNITS 39 l fIN = 1MHz, VIN = 0V to 3V fIN = 100MHz, VIN = 0V to 3V ns 1 ns 0.
PAGE 4
LTC1403-1/LTC1403A-1 DIGITAL INPUTS AND DIGITAL OUTPUTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 3V SYMBOL PARAMETER CONDITIONS VIH High Level Input Voltage VDD = 3.3V l VIL Low Level Input Voltage VDD = 2.7V l 0.
PAGE 5
LTC1403-1/LTC1403A-1 ELECTRICAL CHARACTERISTICS Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND. Note 3: When these pins are taken below GND or above VDD, they will be clamped by internal diodes.
PAGE 6
LTC1403-1/LTC1403A-1 TYPICAL PERFORMANCE CHARACTERISTICS – TA = 25°C, VDD = 3V. Single ended AIN+ signal drive with AIN = 1.5V DC, differential signals drive both inputs with VCM = 1.5V DC (LTC1403A-1) THD, 2nd and 3rd vs Input Frequency SFDR vs Input Frequency –44 104 11.5 71 –50 98 11.0 68 –56 92 –62 86 10.5 65 10.0 62 9.5 59 9.0 56 8.5 53 1 10 FREQUENCY (MHz) THD –74 3rd –80 2nd –86 56 50 1 10 FREQUENCY (MHz) 71 11.5 71 11.0 68 65 10.5 65 10.
PAGE 7
LTC1403-1/LTC1403A-1 TYPICAL PERFORMANCE CHARACTERISTICS – with AIN TA = 25°C, VDD = 3V. Single ended AIN+ signal drive = 1.5V DC, differential signals drive both inputs with VCM = 1.5V DC (LTC1403A-1) 1.4MHz Input Summed with 1.56MHz Input IMD 4096 Point FFT Plot for Differential Input Signals 1.3MHz Sine Wave 4096 Point FFT Plot for Differential Input Signals 0 0 –10 –10 0 –10 –20 –20 –30 –30 –40 –30 –40 –40 –50 –60 –70 –80 MAGNITUDE (dB) –20 MAGNITUDE (dB) MAGNITUDE (dB) 10.
PAGE 8
LTC1403-1/LTC1403A-1 TYPICAL PERFORMANCE CHARACTERISTICS 2.
PAGE 9
LTC1403-1/LTC1403A-1 PIN FUNCTIONS AIN+ (Pin 1): Noninverting Analog Input. AIN+ operates fully differentially with respect to AIN – with a –1.25V to 1.25V differential swing with respect to AIN – and a 0V to VDD common mode swing. solid analog ground plane with a 10µF ceramic capacitor (or 10µF tantalum in parallel with 0.1µF ceramic). Keep in mind that internal analog currents and digital output signal currents flow through this pin. Care should be taken to place the 0.
PAGE 10
LTC1403-1/LTC1403A-1 TIMING DIAGRAM LTC1403-1 Timing Diagram t2 t3 17 18 t7 t1 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 16 17 18 1 SCK t4 t5 CONV t6 INTERNAL S/H STATUS tACQ SAMPLE HOLD SAMPLE t8 t8 SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION Hi-Z SDO D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X* HOLD t9 Hi-Z X* 14031 TD01 14-BIT DATA WORD tCONV tTHROUGHPUT *BITS MARKED "X" AFTER D0 SHOULD BE IGNORED.
PAGE 11
LTC1403-1/LTC1403A-1 APPLICATIONS INFORMATION DRIVING THE ANALOG INPUT The differential analog inputs of the LTC1403-1/LTC1403A‑1 are easy to drive. The inputs may be driven differentially or as a single-ended input (i.e., the AIN – input is set to VCM). Both differential analog inputs, AIN+ with AIN–, are sampled at the same instant. Any unwanted signal that is common to both inputs of each input pair will be reduced by the common mode rejection of the sample-and-hold circuit.
PAGE 12
LTC1403-1/LTC1403A-1 APPLICATIONS INFORMATION INPUT FILTERING AND SOURCE IMPEDANCE The noise and the distortion of the input amplifier and other circuitry must be considered since they will add to the LTC1403-1/LTC1403A-1 noise and distortion. The small-signal bandwidth of the sample-and-hold circuit is 50MHz. Any noise or distortion products that are present at the analog inputs will be summed over this entire bandwidth. Noisy input circuitry should be filtered prior to the analog inputs to minimize noise.
PAGE 13
LTC1403-1/LTC1403A-1 APPLICATIONS INFORMATION internal reference. The recommended range for an external reference is 2.55V to VDD. An external reference at 2.55V will see a DC quiescent load of 0.75mA and as much as 3mA during conversion. INPUT SPAN VERSUS REFERENCE VOLTAGE The differential input range has a unipolar voltage span that equals the difference between the voltage at the reference buffer output VREF at Pin 3, and the voltage at the ground (Exposed Pad Ground).
PAGE 14
LTC1403-1/LTC1403A-1 APPLICATIONS INFORMATION 0 –10 MAGNITUDE (dB) –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 185k 371k 556k FREQUENCY (Hz) 741k 14031 F06b Figure 6b. LTC1403-1 6MHz Sine Wave 4096 Point FFT Plot with the LT1819 Driving the Inputs Differentially Board Layout and Bypassing Wire wrap boards are not recommended for high resolution and/or high speed A/D converters. To obtain the best performance from the LTC1403-1/LTC1403A-1, a printed circuit board with ground plane is required.
PAGE 15
LTC1403-1/LTC1403A-1 APPLICATIONS INFORMATION One or more rising edges at SCK wake up the LTC1403-1/ LTC1403A-1 for service very quickly, and CONV can start an accurate conversion within a clock cycle. Four rising edges at CONV, without any intervening rising edges at SCK, put the LTC1403-1/LTC1403A-1 in Sleep mode and the power drain drops from 16mW to 10µW. One or more rising edges at SCK wake up the LTC1403-1/LTC1403A-1 for operation.
PAGE 16
LTC1403-1/LTC1403A-1 APPLICATIONS INFORMATION the clock to latch data from the Serial Data Output (SDO) into your processor serial port. The 14-bit Serial Data will be received right justified, in a 16-bit word with 16 or more clocks per frame sync. It is good practice to drive the LTC1403-1/LTC1403A-1 SCK input first to avoid digital noise interference during the internal bit comparison decision by the internal high speed comparator.
PAGE 17
LTC1403-1/LTC1403A-1 APPLICATIONS INFORMATION ; ; ; ; ; ; ; ; ; ; ; ; ; 10-23-03 ****************************************************************** Files: 014SI.ASM -> 1403 bipolar Sine wave collection with Serial Port interface bvectors.asm buffered mode. s2k14ini.asm 2k buffer size. first element at 1024, last element at 1023, two middles at 2047 and 0000 bipolar mode Works 16 or 64 clock frames.
PAGE 18
LTC1403-1/LTC1403A-1 APPLICATIONS INFORMATION ; bsend ; —————————dummy bsend return———————————— return _ enable ;this is also a dummy return to define bsend ;in vector table file BVECTORS.ASM ——————————— end ISR —————————————— .copy “c:\dskplus\1403\s2k14ini.asm” ;initialize buffered serial port .
PAGE 19
LTC1403-1/LTC1403A-1 APPLICATIONS INFORMATION int2 tint brint bxint trint txint int3 hpiint return _ enable nop nop nop return _ enable nop nop nop goto breceive nop nop nop goto bsend nop nop nop return _ enable nop nop nop return _ enable nop nop return _ enable nop nop nop dgoto #0e4h nop nop .
PAGE 20
LTC1403-1/LTC1403A-1 APPLICATIONS INFORMATION ***************************************************************************************************** *LTC1403 timing from board with 10MHz crystal. * *10MHz, divided from 40MHz, forced to CLKIN by 1403 board. * *Horizontal scale is 25ns/chr or 100ns period at BCLKR * *Timing measured at DSP pins. Jxx pin labels for jumper cable.
PAGE 21
LTC1403-1/LTC1403A-1 REVISION HISTORY REV DATE DESCRIPTION A 1/10 Revised Pin Configuration PAGE NUMBER 2 B 6/10 Corrected transposed part numbers in Order Information section 2 C 6/12 Corrected output code from natural binary to 2’s complement 13 14031fc Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use.
PAGE 22
LTC1403-1/LTC1403A-1 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. MSE Package 10-Lead Plastic MSOP, Exposed Die Pad (Reference LTC DWG # 05-08-1664 Rev D) 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 10 9 8 7 6 1 DETAIL “A” 1 2 3 4 5 0.53 ± 0.152 (.021 ± .006) DETAIL “A” 0.18 (.007) SEATING PLANE 0.17 – 0.27 (.007 – .011) TYP 10 0.86 (.034) REF 1.10 (.043) MAX 0.50 (.