Datasheet

ManualsBrandsLINEAR TECHNOLOGY ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal QFN 32

LTC1408

1408fa

6 Channel, 14-Bit, 600ksps

Simultaneous Sampling ADC

with Shutdown

The LTC

1408 is a 14-bit, 600ksps ADC with six simulta-

neously sampled differential inputs. The device draws

only 5mA from a single 3V supply, and comes in a tiny 32

pin (5mm × 5mm) QFN package. A SLEEP shutdown

feature lowers power consumption to 6µW. The combina-

tion of low power and tiny package makes the LTC1408

suitable for portable applications.

The LTC1408 contains six separate differential inputs that

are sampled simultaneously on the rising edge of the

CONV signal. These six sampled inputs are then

converted at a rate of 100ksps per channel.

The 90dB common mode rejection allows users to

eliminate ground loops and common mode noise by

measuring signals differentially from the source.

The device converts 0V to 2.5V unipolar inputs differen-

tially, or ±1.25V bipolar inputs also differentially,

depending on the state of the BIP pin. Any analog input

may swing rail-to-rail as long as the differential input

range is maintained.

The conversion sequence can be abbreviated to convert

fewer than six channels, depending on the logic state of

the SEL2, SEL1 and SEL0 inputs.

The serial interface sends out the six conversion results in

96 clocks for compatibility with standard serial interfaces.

■

600ksps ADC with 6 Simultaneously Sampled

Differential Inputs

■

100ksps Throughput per Channel

■

76dB SINAD

■

Low Power Dissipation: 15mW

■

3V Single Supply Operation

■

2.5V Internal Bandgap Reference, Can be Overdriven

with External Reference

■

3-Wire Serial Interface

■

Internal Conversion Triggered by CONV

■

SLEEP (6µW) Shutdown Mode

■

NAP (3.3mW) Shutdown Mode

■

0V to 2.5V Unipolar, or ±1.25V Bipolar Differential

Input Range

■

90dB Common Mode Rejection

■

Tiny 32-Pin (5mm

××

5mm) QFN Package

■

Multiphase Power Measurement

■

Multiphase Motor Control

■

Data Acquisition Systems

■

Uninterruptable Power Supplies

APPLICATIO S

FEATURES

DESCRIPTIO

BLOCK DIAGRA

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All

other trademarks are the property of their respective owners. Protected by U.S. Patents

including 6084440, 6522187.

–

7 6912

1619 8

CH0

–

CH0

CH1

–

CH1

–

1415

CH2

–

CH2

CH3

–

CH3

–

2021

S AND H S AND H S AND H S AND H S AND H

CH4

–

CH4

CH5

–

CH5

MUX

REF

10µF

BIP SEL2 SEL1 SEL0

GND

2.5V

REFERENCE

600ksps

14-BIT ADC

14-BIT LATCH 5

14-BIT LATCH 4

14-BIT LATCH 3

14-BIT LATCH 2

14-BIT LATCH 1

14-BIT LATCH 0

10µF3V

2629232233 27 28

SD0

0.1µF

SCK

DGND

OGND

CONV

THREE-

STATE

SERIAL

OUTPUT

PORT

TIMING

LOGIC

1408 TA01

–

S AND H

Summary of content (20 pages)

PAGE 1
LTC1408 6 Channel, 14-Bit, 600ksps Simultaneous Sampling ADC with Shutdown DESCRIPTIO U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ The LTC®1408 is a 14-bit, 600ksps ADC with six simultaneously sampled differential inputs. The device draws only 5mA from a single 3V supply, and comes in a tiny 32 pin (5mm × 5mm) QFN package. A SLEEP shutdown feature lowers power consumption to 6µW. The combination of low power and tiny package makes the LTC1408 suitable for portable applications.
PAGE 2
LTC1408 U U RATI GS W W W W AXI U U ABSOLUTE PACKAGE/ORDER I FOR ATIO (Notes 1, 2) ORDER PART NUMBER GND CH2+ CH2– GND GND CH3+ GND CH3– TOP VIEW Supply Voltage (VDD, VCC, OVDD) .............................. 4V Analog Input Voltage (Note 3) ................................... – 0.3V to (VDD + 0.3V) Digital Input Voltage .................... – 0.3V to (VDD + 0.3V) Digital Output Voltage .................. – 0.3V to (VDD + 0.3V) Power Dissipation ........................................
PAGE 3
LTC1408 W U DY A IC ACCURACY The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. With internal reference, VDD = 3V, VDD = VCC = 3V. SYMBOL PARAMETER CONDITIONS MIN TYP SINAD Signal-to-Noise Plus Distortion Ratio 100kHz Input Signal 300kHz Input Signal 100kHz Input Signal, External VREF = 3.3V, VDD ≥ 3.3V 300kHz Input Signal, External VREF = 3.3V, VDD ≥ 3.
PAGE 4
LTC1408 U W POWER REQUIRE E TS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. With internal reference, VDD = VCC= 3V. SYMBOL PARAMETER CONDITIONS MIN VDD, VCC Supply Voltage IDD + ICC Supply Current Active Mode, fSAMPLE = 600ksps Nap Mode Sleep Mode PD Power Dissipation Active Mode with SCK, fSAMPLE = 600ksps TYP MAX UNITS 3.6 V 7 1.9 15 mA mA µA 2.7 ● ● 5 1.1 2.
PAGE 5
LTC1408 U W TYPICAL PERFOR A CE CHARACTERISTICS –44 74 12 –50 71 11.5 68 11 65 10.5 59 UNIPOLAR SINGLE ENDED 9.5 56 BIPOLAR DIFFERENTIAL 9 1 10 FREQUENCY (MHz) –68 THD (dB) SINAD (dB) 5 HARMONIC THD –62 8.5 –56 2nd –62 3rd –74 –80 –92 –98 –98 –104 –104 1 10 FREQUENCY (MHz) 76 98 75 0 –10 –20 73 72 74 68 UNIPOLAR SINGLE ENDED 71 70 69 68 62 67 UNIPOLAR SINGLE ENDED –30 –40 –50 –60 –70 –80 –90 66 –100 50 65 –110 44 64 0.
PAGE 6
LTC1408 U W TYPICAL PERFOR A CE CHARACTERISTICS 833kHz into CH0 +, 841kHz into CH0 –, 588ksps Bipolar Mode 4096 Point FFT Differential Linearity for CH0 with Internal 2.5V Reference, Unipolar Mode 0 1.0 –10 0.8 –20 –20 –30 –30 –40 –40 –50 –60 –70 –80 –50 –60 –70 –80 –90 –90 –100 –100 –110 –110 –120 0 62.5 125 188 FREQUENCY(kHz) 250 DIFFERENTIAL LINEARITY (LSB) 0 –10 MAGNITUDE (dB) OUTPUT MAGNITUDE (dB) 610kHz Unipolar Single Ended Input Sine Wave 4096 Point FFT, 625ksps 0.4 0.
PAGE 7
LTC1408 U W TYPICAL PERFOR A CE CHARACTERISTICS VDD = 3V, TA = 25°C Simultaneous Step at all 6 Channels from 25Ω Source Sampling Frequency = 625ksps Input Frequency = 625.
PAGE 8
LTC1408 U U U PI FU CTIO S CH3+ (Pin 14): Non-Inverting Channel 3. CH3+ operates fully differentially with respect to CH3– with a 0V to 2.5V, or ±1.25V differential swing and a 0V to VDD absolute input range. CH3– (Pin 15): Inverting Channel 3. CH3– operates fully differentially with respect to CH3+ with a –2.5V to 0V, or ±1.25V differential swing and a 0V to VDD absolute input range. CH4+ (Pin 17): Non-Inverting Channel 4. CH4+ operates fully differentially with respect to CH4– with a 0V to 2.
PAGE 9
LTC1408 U U U PI FU CTIO S CONV (Pin 30): Convert Start. Holds the six analog input signals and starts the conversion on the rising edge. Two pulses with SCK in fixed high or fixed low state starts Nap mode. Four or more pulses with SCK in fixed high or fixed low state starts Sleep mode. SCK (Pin 32): External Clock Input. Advances the conversion process and sequences the output data at SD0 (Pin1) on the rising edge. One or more pulses wake from sleep or nap power saving modes.
PAGE 10
LTC1408 W UW LTC1408 Timing Diagram TI I G DIAGRA S 1408fa 10
PAGE 11
LTC1408 W UW TI I G DIAGRA S Nap Mode and Sleep Mode Waveforms SCK t1 t1 CONV NAP SLEEP t11 VREF 1408 TD02 NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS SCK to SDO Delay SCK VIH SCK VIH t8 t10 SDO t9 VOH SDO Hi-Z VOL 1408 TD03 1408fa 11
PAGE 12
LTC1408 U W U U APPLICATIO S I FOR ATIO SELECT NUMBER OF CONVERTED CHANNELS (SEL2, SEL1, SEL0) These three control pins select the number of channels being converted. 000 selects only the first channel (CH0) for conversion. Incrementing SELx selects additional channels for conversion, up to 6 channels. 101, 110 or 111 select all 6 channels for conversion. These pins must be kept in a fixed state during conversion and during the subsequent conversion to read data.
PAGE 13
LTC1408 U W U U APPLICATIO S I FOR ATIO CHOOSING AN INPUT AMPLIFIER Choosing an input amplifier is easy if a few requirements are taken into consideration. First, to limit the magnitude of the voltage spike seen by the amplifier from charging the sampling capacitor, choose an amplifier that has a low output impedance (< 100Ω) at the closed-loop bandwidth frequency.
PAGE 14
LTC1408 U W U U APPLICATIO S I FOR ATIO INPUT FILTERING AND SOURCE IMPEDANCE INPUT RANGE The noise and the distortion of the input amplifier and other circuitry must be considered since they will add to the LTC1408 noise and distortion. The small-signal bandwidth of the sample-and-hold circuit is 50MHz. Any noise or distortion products that are present at the analog inputs will be summed over this entire bandwidth. Noisy input circuitry should be filtered prior to the analog inputs to minimize noise.
PAGE 15
LTC1408 U W U U APPLICATIO S I FOR ATIO INPUT SPAN VERSUS REFERENCE VOLTAGE The differential input range has a unipolar voltage span that equals the difference between the voltage at the reference buffer output VREF (Pin 23) and the voltage at ground. The differential input range of the ADC is 0V to 2.5V when using the internal reference. The internal ADC is referenced to these two nodes. This relationship also holds true with an external reference.
PAGE 16
LTC1408 U W U U APPLICATIO S I FOR ATIO POWER-DOWN MODES DIGITAL INTERFACE Upon power-up, the LTC1408 is initialized to the active state and is ready for conversion. The Nap and Sleep mode waveforms show the power down modes for the LTC1408. The SCK and CONV inputs control the power down modes (see Timing Diagrams). Two rising edges at CONV, without any intervening rising edges at SCK, put the LTC1408 in Nap mode and the power drain drops from 15mW to 3.3mW.
PAGE 17
LTC1408 U W U U APPLICATIO S I FOR ATIO Minimizing Jitter on the CONV Input Serial Clock Input (SCK) In high speed applications where high amplitude sinewaves above 100kHz are sampled, the CONV signal must have as little jitter as possible (10ps or less). The square wave output of a common crystal clock module usually meets this requirement easily. The challenge is to generate a CONV signal from this crystal clock without jitter corruption from other digital circuits in the system.
PAGE 18
LTC1408 U W U U APPLICATIO S I FOR ATIO BOARD LAYOUT AND BYPASSING Wire wrap boards are not recommended for high resolution and/or high speed A/D converters. To obtain the best performance from the LTC1408, a printed circuit board with ground plane is required. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track.
PAGE 19
LTC1408 U PACKAGE DESCRIPTIO UH Package 32-Lead Plastic QFN (5mm × 5mm) (Reference LTC DWG # 05-08-1693) 0.70 ±0.05 5.50 ±0.05 4.10 ±0.05 3.45 ±0.05 (4 SIDES) PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC RECOMMENDED SOLDER PAD LAYOUT 5.00 ± 0.10 (4 SIDES) BOTTOM VIEW—EXPOSED PAD PIN 1 NOTCH R = 0.30 TYP OR 0.35 × 45° CHAMFER R = 0.115 TYP 0.75 ± 0.05 0.00 – 0.05 31 32 0.40 ± 0.10 PIN 1 TOP MARK (NOTE 6) 1 2 3.45 ± 0.10 (4-SIDES) (UH32) QFN 1004 0.200 REF NOTE: 1.
PAGE 20
LTC1408 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS ADCs LTC1402 12-Bit, 2.2Msps Serial ADC 5V or ±5V Supply, 4.096V or ±2.5V Span LTC1403/LTC1403A 12-/14-Bit, 2.8Msps Serial ADC 3V, 15mW, Unipolar Inputs, MSOP Package LTC1403-1/LTC1403A-1 12-/14-Bit, 2.