Datasheet

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LTC1415

12-Bit, 1.25Msps, 55mW

Sampling A/D Converter

ITY

1.25MHz, 12-Bit Sampling A/D Converter

, LTC and LT are registered trademarks of Linear Technology Corporation.

Effective Bits and Signal-to-(Noise + Distortion)

vs Input Frequency

■

1.25Msps Sample Rate

■

Single 5V Supply

■

Power Dissipation: 55mW

■

Nap and Sleep Power Shutdown Modes

■

0.35LSB INL and

0.25LSB DNL

■

72dB S/(N + D) and 80dB THD at 100kHz

■

External or Internal Reference Operation

■

True Differential Inputs Reject Common Mode Noise

■

Input Range: 4.096V (1mV/LSB)

■

28-Pin SSOP and SO Packages

ESCRIPTIO

The LTC

1415 is a 700ns, 1.25Msps, 12-bit sampling

A/D converter that draws only 55mW from a single 5V

supply. This easy-to-use device includes a high dynamic

range sample-and-hold, precision reference and a trimmed

internal clock. Two power shutdown modes provide flex-

ibility for low power systems.

The LTC1415’s full-scale input range is 4.096V. Low

linearity errors ±0.35LSB INL, ±0.25LSB DNL make it

ideal for imaging systems. Outstanding AC performance

includes 72dB

S/(N + D) and 80dB THD with an input

frequency of 100kHz.

The unique differential input sample-and-hold can acquire

single-ended or differential input signals up to its 18MHz

bandwidth. The 60dB common mode rejection allows

users to eliminate ground loops and common mode noise

by measuring signals differentially from the source.

The ADC has a µP compatible, 12-bit parallel output port.

There is no pipeline delay in the conversion results. A

separate convert start input and data ready signal (BUSY)

ease connections to FIFOs, DSPs and microprocessors. A

separate output logic supply pin allows direct connection

to 3V components.

–A

REF

REFCOMP

AGND

D11(MSB)

D10

DGND

BUSY

CONVST

SHDN

NAP/SLP

OGND

LTC1415

10µF

DIFFERENTIAL

ANALOG INPUT

(0V TO 4.096V)

2.50V

REF

OUTPUT

10µF

12-BIT

PARALLEL

BUS

µP CONTROL

LINES

1415 TA01

OUTPUT LOGIC

SUPPLY 3V OR 5V

INPUT FREQUENCY (Hz)

EFFECTIVE BITS

SIGNAL/(NOISE + DISTORTION) (dB)

10k 100k

LTC1415 • TA02

1M 2M

NYQUIST

FREQUENCY

SAMPLE

= 1.25Msps

■

High Speed Data Acquisition

■

Imaging Systems

■

Digital Signal Processing

■

Multiplexed Data Acquisition Systems

■

Telecommunications

Summary of content (24 pages)

PAGE 1
LTC1415 12-Bit, 1.25Msps, 55mW Sampling A/D Converter U DESCRIPTIO FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ The LTC®1415 is a 700ns, 1.25Msps, 12-bit sampling A/D converter that draws only 55mW from a single 5V supply. This easy-to-use device includes a high dynamic range sample-and-hold, precision reference and a trimmed internal clock. Two power shutdown modes provide flexibility for low power systems. 1.25Msps Sample Rate Single 5V Supply Power Dissipation: 55mW Nap and Sleep Power Shutdown Modes ±0.
PAGE 2
LTC1415 W U U W W W AXI U U ABSOLUTE PACKAGE/ORDER I FOR ATIO RATI GS AVDD = DVDD =OVDD = VDD (Notes 1, 2) ORDER PART NUMBER TOP VIEW Supply Voltage (VDD) ................................................ 6V Analog Input Voltage (Note 3) ...... – 0.3V to VDD + 0.3V Digital Input Voltage (Note 4) .................. – 0.3V to 12V Digital Output Voltage .................... – 0.3V to VDD + 0.3V Power Dissipation .............................................
PAGE 3
LTC1415 W U DY A IC ACCURACY (Note 5) SYMBOL PARAMETER CONDITIONS S/(N + D) Signal-to-(Noise + Distortion) Ratio 100kHz Input Signal 600kHz Input Signal MIN 72 69 dB dB THD Total Harmonic Distortion 100kHz Input Signal, First 5 Harmonics 600kHz Input Signal, First 5 Harmonics – 80 – 72 dB dB SFDR Spurious Free Dynamic Range 600kHz Input Signal – 75 dB IMD Intermodulation Distortion fIN1 = 29.37kHz, fIN2 = 32.
PAGE 4
LTC1415 WU TI I G CHARACTERISTICS (Note 5) SYMBOL PARAMETER fSAMPLE(MAX) Maximum Sampling Frequency Conversion and Acquisition Time CONDITIONS ● ● MIN tCONV Conversion Time tACQ Acquisition Time t1 CS to RD Setup Time t2 t3 t4 SHDN↑ to CONVST↓ Wake-Up Time Nap Mode (Note 10) Sleep Mode, CREFCOMP = 10µF (Note 10) t5 CONVST Low Time (Notes 10, 11) MAX UNITS 800 MHz ns ● 700 ns ● 150 ns t6 CONVST to BUSY Delay CL = 25pF (Notes 9, 10) ● 0 CS↓ to CONVST↓ Setup Time (Notes 9, 1
PAGE 5
LTC1415 U W TYPICAL PERFORMANCE CHARACTERISTICS S/(N + D) vs Input Frequency and Amplitude Signal-to-Noise Ratio vs Input Frequency 80 AMPLITUDE (dB BELOW THE FUNDAMENTAL) 70 70 60 SIGNAL-TO -NOISE RATIO (dB) SIGNAL/(NOISE + DISTORTION) (dB) VIN = 0dB VIN = –20dB 50 40 30 VIN = –60dB 20 60 50 40 30 20 10 10 0 0 1k 100k 10k INPUT FREQUENCY (Hz) 1M 2M 1k 10k 100k INPUT FREQUENCY (Hz) LTC1415 • TPC01 0 –10 –20 –30 –40 –50 –60 –70 THD 2ND –80 –90 3RD –100 1k 1M 2M 10k 100k INPUT FR
PAGE 6
LTC1415 U W Power Supply Feedthrough vs Ripple Frequency Input Common Mode Rejection vs Input Frequency 0 80 –10 70 COMMON MODE REJECTION (dB) AMPLITUDE OF POWER SUPPLY FEEDTHROUGH (dB) TYPICAL PERFORMANCE CHARACTERISTICS –20 –30 –40 –50 –60 –70 VDD –80 DGND –90 OVDD –100 1k 100k 10k RIPPLE FREQUENCY (Hz) 60 50 40 30 20 10 0 1M 2M LTC1415 • TPC08 1k 10k 100k INPUT FREQUENCY (Hz) 1M 2M LTC1415 • TPC09 U U U PI FU CTIO S + AIN (Pin 1): Positive Analog Input, 0V to 4.096V.
PAGE 7
LTC1415 U U W FU CTIO AL BLOCK DIAGRA CSAMPLE +AIN AVDD CSAMPLE – AIN 2k VREF DVDD ZEROING SWITCHES 2.5V REF + REF AMP COMP 12-BIT CAPACITIVE DAC – REFCOMP (4.
PAGE 8
LTC1415 U U W U APPLICATIONS INFORMATION The LTC1415 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 12-bit parallel output. The ADC is complete with a precision reference and an internal clock. The control logic provides easy interface to microprocessors and DSPs (please refer to Digital Interface section for the data format). Conversion start is controlled by the CS and CONVST inputs.
PAGE 9
LTC1415 U U W U APPLICATIONS INFORMATION Effective Number of Bits The effective number of bits (ENOBs) is a measurement of the resolution of an ADC and is directly related to the S/(N + D) by the equation: N = [S/(N + D) – 1.76]/6.02 where N is the effective number of bits of resolution and S/(N + D) is expressed in dB. At the maximum sampling rate of 1.25MHz the LTC1415 maintains very good ENOBs up to the Nyquist input frequency of 625kHz (refer to Figure 3).
PAGE 10
LTC1415 U W U U APPLICATIONS INFORMATION If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa + – nfb, where m and n = 0, 1, 2, 3, etc. For example, the 2nd order IMD terms include (fa + fb).
PAGE 11
LTC1415 U W U U APPLICATIONS INFORMATION The following list is a summary of the op amps that are suitable for driving the LTC1415, more detailed information is available in the Linear Technology databooks and the LinearViewTM CD-ROM. LT ® 1215/LT1216: Dual and quad 23MHz, 50V/µs single supply op amps. Single 5V to ±15V supplies, 6.6mA specifications, 90ns settling to 0.5LSB. LT1223: 100MHz video current feedback amplifier. ±5V to ±15V supplies, 6mA supply current. Low distortion up to and above 400kHz.
PAGE 12
LTC1415 U U W U APPLICATIONS INFORMATION circuitry. The reference amplifier gains the voltage at the VREF pin by 1.638 to create the required internal reference voltage of 4.096V. This provides buffering between the VREF pin and the high speed capacitive DAC. The reference amplifier compensation pin (REFCOMP, Pin 4) must be bypassed with a capacitor to ground. The reference amplifier is stable with capacitors of 1µF or greater.
PAGE 13
LTC1415 U U W U APPLICATIONS INFORMATION 4.096V to 2.048V and shifts the common mode voltage from half of full scale to 2.274V. AC Coupled Inputs The analog inputs can be AC coupled for applications where the input has no DC information. The input of the ADC does need to be DC biased at midscale. Figures 10d and 10e demonstrate AC coupling and the required biasing. Figure 10d shows the ADC with a full scale of 4.096V, a common mode voltage of 2.048V and an input that swings from 0V to 4.096V.
PAGE 14
LTC1415 U W U U APPLICATIONS INFORMATION limitations at high input frequencies (THD = 75dB at 600kHz). The ADC in Figure 10e has a full scale of 2.048V and a common mode of 2.27V. The reduced signal swing of this circuit results in improved distortion at higher input frequencies (THD = 82dB at 600kHz) but with worse SINAD at low frequencies (SINAD = 70dB at 100kHz).
PAGE 15
LTC1415 U U W U APPLICATIONS INFORMATION width for these tracks should be as wide as possible. In applications where the ADC data outputs and control signals are connected to a continuously active microprocessor bus, it is possible to get errors in the conversion results. These errors are due to feedthrough from the microprocessor to the successive approximation comparator.
PAGE 16
TAB 4 GND 2 VCC RD SHDN NAP/SLP JP4B JP4A 4 JP4C U5B HC14 CS 23 JP3 3 JP4D R13 51Ω 1 U5A HC14 C5 1µF 16V R20 10k R19 10k C10 10µF 16V VOUT VIN AGND DGND 1 R16 51Ω C8 1000pF R15 51Ω R17 1M + VCC C1 22µF 10V R18 1M C4 1000pF C3 1000pF C6 10µF 16V D15 SS12 VCC 3.
PAGE 17
LTC1415 U W U U APPLICATIONS INFORMATION Figure 13b. Suggested Evaluation Circuit Board Component Side Silkscreen Figure 13c.
PAGE 18
LTC1415 U W U U APPLICATIONS INFORMATION Figure 13d. Suggested Evaluation Circuit Board Solder Side Layout DIGITAL INTERFACE The A/D converter is designed to interface with microprocessors as a memory mapped device. The CS and RD control inputs are common to all peripheral memory interfacing. A separate CONVST is used to initiate a conversion.
PAGE 19
LTC1415 W U U UO APPLICATI S I FOR ATIO In slow memory and ROM modes (Figures 19 and 20) CS is tied low and CONVST and RD are tied together. The MPU starts the conversion and reads the output with the RD signal. Conversions are started by the MPU or DSP (no external sample clock). SHDN t4 CONVST 1415 F14b Figure 14b. SHDN to CONVST Wake-Up Timing Timing and Control Conversion start and data read operations are controlled by three digital inputs: CONVST, CS and RD.
PAGE 20
LTC1415 U W U UO APPLICATI S I FOR ATIO tCONV t8 t5 t13 CONVST t6 t6 t6 BUSY t7 DATA (N – 1) DB11 TO DB0 DATA DATA N DB11 TO DB0 DATA (N + 1) DB11 TO DB0 1415 • F17 Figure 17. Mode 1b CONVST Starts a Conversion. Data is Read by RD t13 tCONV t5 t8 CONVST t6 BUSY t9 t 11 t 12 RD t 10 DATA DATA N DB11 TO DB0 1415 F18 Figure 18. Mode 2 CONVST Starts a Conversion.
PAGE 21
LTC1415 W U U UO APPLICATI S I FOR ATIO t8 t CONV RD = CONVST t 11 t6 BUSY t 10 t7 DATA (N – 1) DB11 TO DB0 DATA DATA N DB11 TO DB0 DATA N DB11 TO DB0 DATA (N + 1) DB11-DB0 1415 • F19 Figure 19. Slow Memory Mode Timing CS = 0 t CONV t8 RD = CONVST t6 t 11 BUSY t 10 DATA DATA N DB11 TO DB0 DATA (N – 1) DB11 TO DB0 1415 • F20 Figure 20.
PAGE 22
LTC1415 U PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. G Package 28-Lead Plastic SSOP (0.209) (LTC DWG # 05-08-1640) 0.397 – 0.407* (10.07 – 10.33) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 0.301 – 0.311 (7.65 – 7.90) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0.205 – 0.212** (5.20 – 5.38) 0.068 – 0.078 (1.73 – 1.99) 0° – 8° 0.005 – 0.009 (0.13 – 0.22) 0.022 – 0.037 (0.55 – 0.95) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.
PAGE 23
LTC1415 U PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. SW Package 28-Lead Plastic Small Outline (Wide 0.300) (LTC DWG # 05-08-1620) 0.697 – 0.712* (17.70 – 18.08) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 0.394 – 0.419 (10.007 – 10.643) NOTE 1 0.291 – 0.299** (7.391 – 7.595) 1 2 3 4 5 6 7 8 9 10 0.093 – 0.104 (2.362 – 2.642) 0.010 – 0.029 × 45° (0.254 – 0.737) 11 12 13 14 0.037 – 0.045 (0.940 – 1.143) 0° – 8° TYP 0.009 – 0.013 (0.
PAGE 24
LTC1415 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1273/75/76 Complete 5V Sampling 12-Bit ADCs with 70dB SINAD at Nyquist Lower Power 75mW and Cost Effective for fSAMPLE ≤ 300ksps LTC1274/77 Low Power 12-Bit ADCs with Nap and Sleep Mode Shutdown Lowest Power (10mW) for fSAMPLE ≤ 100ksps LTC1278/79 High Speed Sampling 12-Bit ADCs with Shutdown Cost Effective 12-Bit ADCs with Convert Start Input Best for 300ksps < fSAMPLE ≤ 600ksps LTC1282 Complete 3V 12-Bit ADC with 12mW Power Dissipation