LTC1417 Low Power 14-Bit, 400ksps Sampling ADC Converter with Serial I/O U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO The LTC ®1417 is a low power, 400ksps, 14-bit A/D converter. This versatile device can operate from a single 5V or ±5V supplies. An onboard high performance sample-andhold, a precision reference and internal trimming minimize external circuitry requirements. The low 20mW power dissipation is made even more attractive with two userselectable power shutdown modes.
LTC1417 U U RATI GS W W W W AXI U PACKAGE/ORDER I FOR ATIO (Notes 1, 2) Positive Supply Voltage (VDD) .................................. 6V Negative Supply Voltage (VSS) Bipolar Operation Only .......................... – 6V to GND Total Supply Voltage (VDD to VSS) Bipolar Operation Only ....................................... 12V Analog Input Voltage (Note 3) Unipolar Operation .................. – 0.3V to (VDD + 0.3V) Bipolar Operation............ (VSS – 0.3) to (VDD + 0.
LTC1417 U U A ALOG I PUT The ● indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
LTC1417 U W POWER REQUIRE E TS The ● indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP UNITS 5.25 V VDD Positive Supply Voltage (Notes 10, 11) VSS Negative Supply Voltage (Note 10) Bipolar Only (VSS = 0V for Unipolar) IDD Positive Supply Current Unipolar, RD High (Note 5) Bipolar, RD High (Note 5) SHDN = 0V, RD = 0V SHDN = 0V, RD = 5V ● ● 4.0 4.3 750 0.1 5.5 6.
LTC1417 WU TI I G CHARACTERISTICS The ● indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN tH SCLK SCLK High Time (Note 9) ● 10 ns tL SCLK SCLK Low Time (Note 9) ● 10 ns tH EXTCLKIN EXTCLKIN High Time ● 0.04 tL EXTCLKIN EXTCLKIN Low Time ● 0.
LTC1417 U W TYPICAL PERFOR A CE CHARACTERISTICS (TA = 25°C, unless otherwise specified) Signal-to-Noise Ratio vs Input Frequency 70 60 50 40 30 20 10 0 10k 100k INPUT FREQUENCY (Hz) – 20 – 40 – 60 – 80 THD –100 3RD –120 1M 2ND 1 –80 –100 1k 200 Intermodulation Distortion Plot 0 –40 – 40 –60 –80 –120 –100 –120 0 50 VDD DGND 120 Input Offset Voltage Shift vs Source Resistance 10 60 50 40 30 20 10 10M 1417 G10 9 8 7 6 5 4 3 2 1 0 0 10k 100k 1M RIPPLE FREQUENCY (Hz) 20 40 60 80 100 120
LTC1417 U W TYPICAL PERFOR A CE CHARACTERISTICS (TA = 25°C, unless otherwise specified) VDD Supply Current vs Temperature (Bipolar Mode) 3.0 5 5 2.5 4 3 2 1 VSS SUPPLY CURRENT (mA) 6 0 –75 –50 –25 4 3 2 1 0 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 4.0 4.0 2.0 1.5 1.0 0 25 50 75 100 125 150 TEMPERATURE (°C) VSS Supply Current vs Sampling Frequency (Bipolar Mode) 2.5 3.5 3.0 2.5 2.0 1.5 1.0 2.0 1.5 1.0 0.5 0.5 0.5 0 0.5 1417 G15 VSS SUPPLY CURRENT (mA) 4.
LTC1417 U U U PIN FUNCTIONS CONVST (Pin 13): Conversion Start Signal. This active low signal starts a conversion on its falling edge. BUSY (Pin 14): The BUSY output shows the converter status. It is low when a conversion is in progress. VSS (Pin 15): Negative Supply, –5V for Bipolar Operation. Bypass to AGND using 10µF tantalum in parallel with 0.1µF ceramic. Analog ground for unipolar operation. VDD (Pin 16): 5V Positive Supply. Bypass to AGND with 10µF tantalum in parallel with 0.1µF ceramic.
LTC1417 U U W U APPLICATIONS INFORMATION The LTC1417 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 14-bit serial output. The ADC is complete with a precision reference and an internal clock. The control logic provides easy interface to microprocessors and DSPs (please refer to Digital Interface section for the data format). Conversion start is controlled by the CONVST input.
LTC1417 U W U U APPLICATIONS INFORMATION 0 fSAMPLE = 400kHz fIN = 10.05859375kHz SFDR = –97.44dB SINAD = 81.71dB AMPLITUDE (dB) –20 –40 –60 The effective number of bits (ENOBs) is a measurement of the resolution of an ADC and is directly related to the S/(N + D) by the equation: ENOB (N) = [S/(N + D) – 1.76]/6.02 –80 –100 –120 Effective Number of Bits 0 50 100 150 FREQUENCY (kHz) 200 where N is the effective number of bits of resolution and S/(N + D) is expressed in dB.
LTC1417 U U W U AMPLITUDE (dB BELOW THE FUNDAMENTAL) APPLICATIONS INFORMATION ( 0 – 20 – 40 ) Amplitude at fa The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full-scale input signal. – 80 THD –100 3RD 2ND 1 10 100 INPUT FREQUENCY (kHz) 1000 1417 G05 Figure 5.
LTC1417 U W U U APPLICATIONS INFORMATION LT1360: 50MHz Voltage Feedback Amplifier. 3.8mA supply current, ±2.5V to ±15V supplies. High AVOL, 1mV offset and 80ns settling to 1mV (4V step, inverting and noninverting configurations) make it suitable for fast DC applications. Excellent AC specifications. Dual and quad versions are available as LT1361 and LT1362. ACQUISITION TIME (µs) 100 10 1 LT1468: 90MHz Voltage Feedback Amplifier. ±5V to ±15V supplies. Lower distortion and noise. Settles to 0.
LTC1417 U U W U APPLICATIONS INFORMATION capacitor from + AIN to ground and a 100Ω source resistor to limit the input bandwidth to 1.6MHz. The 1000pF capacitor also acts as a charge reservoir for the input sample-and-hold and isolates the ADC input from sampling glitch sensitive circuitry. High quality capacitors and resistors should be used since these components can add distortion. NPO and silver mica type dielectric capacitors have excellent linearity.
LTC1417 U U W U APPLICATIONS INFORMATION Unipolar Offset and Full-Scale Error Adjustment Bipolar Offset and Full-Scale Error Adjustment In applications where absolute accuracy is important, offset and full-scale errors can be adjusted to zero. Offset error must be adjusted before full-scale error. Figures 11a and 11b show the extra components required for fullscale error adjustment. Zero offset is achieved by adjusting the offset applied to the AIN– input. For zero offset error, apply 125µV (i.e., 0.
LTC1417 U U W U APPLICATIONS INFORMATION 1 AIN+ AIN– ANALOG INPUT CIRCUITRY + – 2 DIGITAL SYSTEM LTC1417 VREF REFCOMP 3 4 1µF AGND VDD VSS 5 15 10µF DGND 16 10 10µF 10µF ANALOG GROUND PLANE 1417 F12 Figure 12. Power Supply Grounding Practice wait state during conversion or by using three-state buffers to isolate the ADC data bus. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible.
LTC1417 U U W U APPLICATIONS INFORMATION C1 0.1µF C2 0.1µF 5A U3 LT1363CN8 R1 10k C3 1000pF 50V R4 75Ω J2 BNC R2 10k 2 3 JP3 C6 1µF 4 C7 10µF 16V + 5 6 7 8 –AIN VSS VREF BUSY AGND EXTCLKIN SCK CLKOUT C8 5A 10µF 16V C9 10µF 16V AGND DGND –5A JP7 U2A TC74HCT244AF 1 2 18 19 VDD CONVST RD SHDN DGND DOUT E3 –5V + 16 15 12 9 1 3 13 10 –5A C11 10µF 16V U2B 14 11 5A C10 10µF 16V E2 GND –5A +AIN REFCOMP 8 C5 0.1µF U1 LTC1417CGN 1 6 4 OPTIONAL + 1 – C4 0.
LTC1417 U W U U APPLICATIONS INFORMATION DIGITAL INTERFACE status is indicated by the BUSY output. BUSY is low during a conversion. The LTC1417 operates in serial mode. The RD control input is common to all peripheral memory interfacing. Only four digital interface lines are required, SCLK, CONVST, EXTCLKIN and DOUT. SCLK, the serial data shift clock can be an external input or supplied by the LTC1417’s internal clock. Data Output Output will be active when RD is low.
LTC1417 U U W U APPLICATIONS INFORMATION Conversion Clock Selection In Figure 15, the conversion clock controls the internal ADC operation. The conversion clock can be either internal or external. By connecting EXTCLKIN high, the internal clock is selected. This clock generates 16 clock cycles which feed into the SAR for each conversion. To select an external conversion clock, apply an external conversion clock to EXTCLKIN (Pin 6).
LTC1417 U U W U APPLICATIONS INFORMATION Serial Data Output During a Conversion conversion time; consequently, this mode can provide the best overall speed performance. To select the internal conversion clock, tie EXTCLKIN (Pin 6) high. The internal clock appears on CLKOUT (Pin 8) which can be tied to SCLK (Pin 7) to supply the SCLK. Using Internal Clock for Conversion and Data Transfer.
LTC1417 U U W U APPLICATIONS INFORMATION Using External Clock for Conversion and Data Transfer. In Figure 18, data from the previous conversion is output during the conversion with an external clock providing both the conversion clock and the shift clock. To select an external conversion clock, apply the clock to EXTCLKIN. The same clock is also applied to SCLK to provide a data CONVST 13 CONVST BUSY shift clock.
LTC1417 U U W U APPLICATIONS INFORMATION Serial Data Output After a Conversion Using an Internal Conversion Clock and an External Data Clock. In this mode, data is output after the end of each conversion and before the next conversion is started (Figure 19). The internal clock is used as the conversion clock and an external clock is used for the SCLK. This mode is useful in applications where the processor acts as a serial bus master device.
LTC1417 U U W U APPLICATIONS INFORMATION Using an External Conversion Clock and an External Data Clock. In Figure 20, data is also output after each conversion is completed and before the next conversion is started. An external clock is used for the conversion clock and either another or the same external clock is used for the SCLK. This mode is identical to Figure 19 except that an external clock is used for the conversion.
LTC1417 U TYPICAL APPLICATIONS Figure 21 shows the connections necessary for interfacing the LTC1417 and LTC1391 8-channel signal acquisition system to an SPI port. With the sample software routine shown in Listing A, the SPI uses MOSI to send serial data to the LTC1391 8-channel multiplexer, selecting one of eight MUX channels. While data is sent to the LTC1391, SPI uses MISO to retrieve conversion data from the LTC1417.
LTC1417 U TYPICAL APPLICATIONS Listing A *********************************************************************** * * * This example program retrieves data from a previous LTC1417 * * conversion and loads the next LTC1391 MUX channel. It stores the * * 14-bit, right justified data in two consecutive memory locations. * * It finishes by initiating the next conversion.
LTC1417 U TYPICAL APPLICATIONS * (This assumes an E-Clock frequency of 4MHz. For higher * E-Clock frequencies, change the above value of $50 to a * value that ensures the SCK frequency is 2MHz or less.
LTC1417 U TYPICAL APPLICATIONS * ***************************************** * Initiate a LTC1417 conversion * ***************************************** * BCLR PORTC,Y %00000001 This sets PORTC, Bit0 output to a logic * low, initiating a conversion BSET PORTC,Y %00000001 This resets PORTC, Bit0 output to a logic * high, returning CONVST to a logic high * PULA Restore the A register PULY Restore the Y register PULX Restore the X register RTS CONVST BUSY RD MUX DATA CH1 CH2 CH3 CH4 CH5 ADC DATA CH7
LTC1417 U TYPICAL APPLICATIONS Figure 23 uses the DG408 to select one of eight ±2.048V bipolar signals and apply it to the LTC1417’s analog input. The circuit is designed to connect to a 68HC11 µC. The MUX’s parallel input is connected to the controller’s port C and the LTC1417’s serial interface is accessed through the controller’s SPI interface. 5V The sequence to generate a conversion is shown in sample program Listing B. The first step selects a MUX channel.
LTC1417 U TYPICAL APPLICATIONS Listing B ************************************************************************* * * * This example program selects a DG408 MUX channel using parallel * * port C, initiates a conversion, and retrieves data from the LTC1417. * * It stores the 14-bit, right justified data in two consecutive memory * * locations.
LTC1417 U TYPICAL APPLICATIONS * E-Clock frequencies, change the above value of $50 to a * value that ensures the SCK frequency is 2MHz or less.
LTC1417 U TYPICAL APPLICATIONS BCLR * TRFLP1 LDAA STAA * WAIT1 LDAA * BPL * * LDAA * STAA INX CPX BNE * BSET * LDD * LSRD LSRD * STD PULA PULY PULX RTS PORTD,Y %00100000 This sets the SS* output bit to a logic low, selecting the LTC1417 #$0 Load accumulator A with a null byte for SPI transfer SPDR This writes the byte into the SPI data register and starts the transfer SPSR This loop waits for the SPI to complete a serial transfer/exchange by reading the SPI Status Register WAIT1 The SPIF (SPI transfer c
LTC1417 U PACKAGE DESCRIPTIO GN Package 16-Lead Plastic SSOP (Narrow 0.150) (LTC DWG # 05-08-1641) 0.189 – 0.196* (4.801 – 4.978) 16 15 14 13 12 11 10 9 0.229 – 0.244 (5.817 – 6.198) 0.150 – 0.157** (3.810 – 3.988) 1 0.015 ± 0.004 × 45° (0.38 ± 0.10) 0.007 – 0.0098 (0.178 – 0.249) 0.009 (0.229) REF 2 3 4 5 6 0.053 – 0.068 (1.351 – 1.727) 7 8 0.004 – 0.0098 (0.102 – 0.249) 0° – 8° TYP 0.016 – 0.050 (0.406 – 1.270) 0.008 – 0.012 (0.203 – 0.305) 0.025 (0.
LTC1417 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS ADCs LTC1274/LTC1277 Low Power, 12-Bit, 100ksps ADCs with Parallel Output 10mW Power Dissipation, Parallel/Byte Interface LTC1401 Serial 3V, 12-Bit, 200ksps ADC in SO-8 15mW, Internal Reference and Low Power Shutdown Mode LTC1404 Serial 12-Bit, 600ksps ADC is SO-8 5V or ±5V, Internal Reference and Shutdown LTC1412 12-Bit, 3Msps Sampling ADC with Parallel Output Best Dynamic Performance, SINAD = 72dB at Nyquist LTC1415 Single 5V, 12-Bit,
