Datasheet

5
LTC1448
W
IDAGRA
B
L
O
C
K
24-BIT
SHIFT
REGISTER
POWER-ON
RESET
LD
DAC B
REGISTER
LD
DAC A
REGISTER
12-BIT
DAC A
–
+
–
+
8
V
OUT B
7
V
CC
6
GND
5
V
OUT A
12-BIT
DAC B
1
2
3
4
CLK
D
IN
CS/LD
REF
1448 BD
TI I G DIAGRA S
UW
W
CLK
D
IN
CS/LD
t
8
t
4
t
3
t
5
B11-A
MSB
B0-A
LSB
B11-B
MSB
B0-B
LSB
t
2
t
1
t
6
t
7
B0-B
PREVIOUS WORD
1448 TD02
D
IN
CLK
CS/LD
1
2
3
4
56789101112131415161718192021222324
DAC B INPUTDAC A INPUT
1448 TD01
D11 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0D10 D11 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0D10
(UPDATE DAC OUTPUT)
(ENABLE CLOCK)
OPERATING SEQUENCE
MSB MSBLSB LSB