Datasheet

ManualsBrandsLINEAR TECHNOLOGY ManualsData collecting ICsData acquisition IC - DA converter (DAC) SOIC 8

LTC1456

12-Bit Rail-to-Rail

Micropower DAC

with Clear Input

■

Digital Calibration

■

Industrial Process Control

■

Automatic Test Equipment

■

Cellular Telephones

APPLICATIONS

TYPICAL APPLICATION

CODE

DNL ERROR (LSB)

0.5

–0.5

1024 2048 2560

1456 TA02

512 1536 3072 3584

4095

Differential Nonlinearity

vs Input Code

Functional Block Diagram: 12-Bit Rail-to-Rail DAC with Clear Input

–

12-BIT

DAC

4.5V TO 5.5V

2.048V

GND

POWER-ON

RESET

OTHER

DACS

12-BIT

SHIFT

REG

AND

DAC

LATCH

µP

OUT

1456 TA01

CLK1

CS/LD3

CLR6

RAIL-TO-RAIL

VOLTAGE

OUTPUT

OUT

FEATURES

■

SO-8 Package

■

12-Bit Resolution

■

Buffered True Rail-to-Rail Voltage Output

■

Asynchronous Clear Input

■

Built-In Reference

■

Schmitt Trigger On Clock Input Allows Direct

Optocoupler Interface

■

Power-On Reset Clears DAC to 0V

■

3-Wire Cascadable Serial Interface

■

Maximum DNL Error: 0.5LSB

■

Low Cost

The LTC

1456 is a complete single supply, rail-to-rail

voltage output, 12-bit digital-to-analog converter (DAC) in

an SO-8 package. It includes a rail-to-rail output buffer

amplifier and an easy-to-use 3-wire cascadable serial

interface. The LTC1456 includes a CLR pin that asynchro-

nously clears the DAC to zero scale.

The LTC1456 has an internal 2.048V reference and a full-

scale output of 4.095V. It operates on a 4.5V to 5.5V

supply, dissipating 2.2mW.

The low power supply current and the space saving SO-8

package make the LTC1456 ideal for battery-powered

applications.

DESCRIPTION

, LTC and LT are registered trademarks of Linear Technology Corporation.

Summary of content (8 pages)

PAGE 1
LTC1456 12-Bit Rail-to-Rail Micropower DAC with Clear Input U DESCRIPTION FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ The LTC®1456 is a complete single supply, rail-to-rail voltage output, 12-bit digital-to-analog converter (DAC) in an SO-8 package. It includes a rail-to-rail output buffer amplifier and an easy-to-use 3-wire cascadable serial interface. The LTC1456 includes a CLR pin that asynchronously clears the DAC to zero scale.
PAGE 2
LTC1456 W U U W W W VCC to GND .............................................. – 0.5V to 7.5V Logic Inputs to GND ................................ – 0.5V to 7.5V VOUT .............................................. – 0.5V to VCC + 0.5V Maximum Junction Temperature ......... – 65°C to 125°C Operating Temperature Range LTC1456C ............................................ 0°C to 70°C LTC1456I ........................................ – 40°C to 85°C Storage Temperature Range ................
PAGE 3
LTC1456 ELECTRICAL CHARACTERISTICS VCC = 4.5V to 5.5V, VOUT unloaded, TA = TMIN to TMAX, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 0.8 V Digital I/O VIH Digital Input High Voltage ● VIL Digital Input Low Voltage ● VOH Digital Output High Voltage VOL ILEAK CIN 2.4 V IOUT = – 1mA, DOUT Only ● VCC – 1.0 V Digital Output Low Voltage IOUT = 1mA, DOUT Only ● 0.
PAGE 4
LTC1456 U W TYPICAL PERFORMANCE CHARACTERISTICS Differential Nonlinearity (DNL) 0.5 2.0 0.4 1.6 1.4 0 – 0.1 – 0.2 VCC – VOUT (V) 0.1 1.0 0.8 INL ERROR (LSB) 0.2 0.4 0 – 0.4 – 0.8 – 0.3 –1.2 – 0.4 –1.6 0 0 512 1024 1536 2048 2560 3072 3584 4095 CODE 125°C Output Swing vs Load Resistance CODE: ALL 0s ALL DIGITAL INPUTS TIED TOGETHER 1.615 600 4.0 25°C – 55°C 200 100 1.210 1.075 0.940 0.805 0 2 0 0 0.5 1 1.5 2 2.5 3 3.
PAGE 5
LTC1456 U U U PIN FUNCTIONS CLK (Pin 1): The Serial Interface Clock. Internal Schmitt trigger on this input allows direct optocoupler interface. DOUT (Pin 4): The Output of the Shift Register Which Becomes Valid on the Rising Edge of the Serial Clock. DIN (Pin 2): The Serial Interface Data. Data on the DIN pin is latched into the shift register on the rising edge of the serial clock. GND (Pin 5): Ground. CS/LD (Pin 3): The Serial Interface Enable and Load Control.
PAGE 6
LTC1456 U U DEFI ITIO S Resolution (n): Resolution is defined as the number of digital input bits, n. It defines the number of DAC output states (2n) that divide the full-scale range. The resolution does not imply linearity. Full-Scale Voltage (VFS): This is the output of the DAC when all bits are set to 1. Voltage Offset Error (VOS): The theoretical voltage at the output when the DAC is loaded with all zeros.
PAGE 7
LTC1456 U OPERATIO Serial Interface The data on the DIN input is loaded into the shift register on the rising edge of the clock. The MSB is loaded first. The DAC register loads the data from the shift register when CS/LD is pulled high. The CLK is disabled internally when CS/LD is high. Note: CLK must be low before CS/LD is pulled low to avoid an extra internal clock pulse. When CLR is pulled low it asynchronously resets the shift and DAC registers to all zeros.
PAGE 8
LTC1456 U PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. N8 Package 8-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510) 0.300 – 0.325 (7.620 – 8.255) 0.009 – 0.015 (0.229 – 0.381) ( +0.025 0.325 –0.015 +0.635 8.255 –0.381 ) 0.045 – 0.065 (1.143 – 1.651) 0.400* (10.160) MAX 0.130 ± 0.005 (3.302 ± 0.127) 0.065 (1.651) TYP 8 7 6 5 1 2 3 4 0.255 ± 0.015* (6.477 ± 0.381) 0.125 (3.175) MIN 0.005 (0.127) MIN 0.018 ± 0.003 0.100 ± 0.010 (0.457 ± 0.076) (2.