Datasheet

5
LTC1481
1481fa
Figure 6. Driver Enable and Disable Times
1.5V
2.3V
2.3V
t
ZH(SHDN)
, t
ZH
t
ZL(SHDN)
, t
ZL
1.5V
t
LZ
0.5V
0.5V
t
HZ
OUTPUT NORMALLY LOW
OUTPUT NORMALLY HIGH
3V
0V
DE
5V
V
OL
V
OH
0V
A, B
A, B
LTC1481 • F06
f = 1MHz, t
r
≤ 10ns, t
f
≤ 10ns
Figure 5. Driver Propagation Delays
DI
3V
1.5V
t
PLH
t
r
t
SKEW
1/2 V
O
V
O
f = 1MHz, t
r
≤ 10ns, t
f
≤ 10ns
90%
10%
0V
B
A
V
O
–V
O
0V
90%
1.5V
t
PHL
t
SKEW
1/2 V
O
10%
t
f
V
DIFF
= V(A) – V(B)
LTC1481 • F05
OUTPUT
UNDER TEST
C
L
S1
S2
V
CC
500Ω
LTC1481 • F04
3V
DE
A
B
DI
R
DIFF
C
L1
C
L2
RO
15pF
A
B
RE
LTC1481 • F03
V
OD
A
B
R
R
V
OC
LTC1481 • F01
RECEIVER
OUTPUT
C
RL
1k
S1
S2
TEST POINT
V
CC
1k
LTC1481 • F02
Figure 2. Receiver Timing Test Load
Figure 4. Driver Timing Test Load
Figure 1. Driver DC Test Load
Figure 3. Driver/Receiver Timing Test Circuit
TEST CIRCUITS
SWITCHI G TI E WAVEFOR S
UWW