Datasheet

8
LTC1685
A
B
1685 F09
≥22k
3.3V
≥22k
3.3V
DE = 0, RE = 0 OR 1
V
DD
= 5V
V
DD
= 0V
A
B
≥22k
≥22k
APPLICATIONS INFORMATION
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Theory of Operation
Unlike typical CMOS transceivers whose propagation
delay can vary by as much as 500% from package to
package and show significant temperature drift, the
LTC1685 employs a novel architecture that produces a
tightly controlled and temperature compensated propaga-
tion delay. The differential timing skew is also minimized
between rising and falling output edges of the receiver
output and the complementary driver outputs.
The precision timing features of the LTC1685 reduce
overall system timing constraints by providing a narrow
±3.5ns window during which valid data appears at the
receiver/driver output. The driver and receiver pair will
have propagation delays that typically match to within 1ns.
In clocked data systems, the low skew minimizes duty
cycle distortion of the clock signal. The LTC1685 can be
used at data rates of 52Mbps with less than 5% duty cycle
distortion (depending on cable length). When a clock
signal is used to retime parallel data, the maximum recom-
mended data transmission rate is 26Mbps to avoid timing
errors due to clock distortion.
Fail-Safe Features
The LTC1685 has a fail-safe feature that guarantees the
receiver output to be in a logic HIGH state when the inputs
are either shorted or left open (note that when inputs are
left open, large external leakage currents might override
the fail-safe circuitry). In order to maintain good high
frequency performance, it was necessary to slow down
the transient response of the fail-safe feature. When a line
fault is detected, the output will go HIGH typically in 2µs.
Note that the LTC1685 guarantees fail-safe performance
over the entire (–7V to 12V) common mode range!
When the inputs are accidentally shorted (by cutting
through a cable, for example), the short circuit fail-safe
feature will guarantee a high output logic level. Note also
that if the line driver is removed and the termination
resistors are left in place, the receiver will see this as a
“short” and output a logic HIGH. Both of these fail-safe
features will keep the receiver from outputting false data
pulses under line fault conditions.
Thermal shutdown and short-circuit protection prevent
latchup damage to the LTC1685 during fault conditions.
Figure 9. Input Thevenin Equivalent
EQUIVALENT INPUT NETWORKS
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