Datasheet

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LTC1852/LTC1853

18523fa

BLOCK DIAGRAM

FEATURES

APPLICATIONS

DESCRIPTION

8-Channel, 10-Bit/12-Bit,

400ksps, Low Power, Sampling ADCs

The 10-bit LTC

1852 and 12-bit LTC1853 are complete

8-channel data acquisition systems. They include a ﬂ exible

8-channel multiplexer, a 400ksps successive approxima-

tion analog-to-digital converter, an internal reference and a

parallel output interface. The multiplexer can be conﬁ gured

for single-ended or differential inputs, two gain ranges and

unipolar or bipolar operation. The ADCs have a scan mode

that will repeatedly cycle through all 8 multiplexer channels

and can also be programmed to sequence through up to

16 addresses and conﬁ gurations. The sequence can also

be read back from internal memory.

The reference and buffer ampliﬁ er provide pin strappable

ranges of 4.096V, 2.5V and 2.048V. The parallel output

includes the 10-bit or 12-bit conversion result plus the

4-bit multiplexer address. The digital outputs are pow-

ered from a separate supply allowing for easy interface

to 3V digital logic. Typical power consumption is 10mW

at 400ksps from a single 5V supply and 3mW at 250ksps

from a single 3V supply.

Flexible 8-Channel Multiplexer

Single-Ended or Differential Inputs

Two Gain Ranges

Unipolar or Bipolar Operation

Scan Mode and Programmable Sequencer

Eliminate Conﬁ guration Software Overhead

Low Power: 3mW at 250ksps

2.7V to 5.5V Supply Range

Internal or External Reference Operation

Parallel Output Includes MUX Address

Nap and Sleep Shutdown Modes

Pin Compatible up-grade 1.25Msps 10-Bit LTC1850

and 12-Bit LTC1851

High Speed Data Acquisition

Test and Measurement

Imaging Systems

Telecommunications

Industrial Process Control

Spectrum Analysis

BUSY

DIFF

OUT

/S6

OUT

/S5

OUT

/S4

OUT

/S3

D11/S2

D10/S1

D9/S0

SHDN

CONVST

DIFF

UNI/BIP

PGA

OUTPUT

DRIVERS

DATA

LATCHES

OGND

18523 BD

REF AMP

REFCOMP

REFIN

REFOUT

COM

CH7

CH6

CH5

CH4

CH3

CH2

CH1

CH0

8-CHANNEL

MULTIPLEXER

2.5V

REFERENCE

INTERNAL

CLOCK

LTC1853

CONTROL LOGIC

AND

PROGRAMMABLE

SEQUENCER

12-BIT

SAMPLING

ADC

–

Integral Linearity

0 512 1024 1536 2048 2560 3072 3584 4096

CODE

1.0

0.5

–0.5

–1.0

INL ERROR (LSBs)

1852 F01

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

Summary of content (24 pages)

PAGE 1
LTC1852/LTC1853 8-Channel, 10-Bit/12-Bit, 400ksps, Low Power, Sampling ADCs FEATURES DESCRIPTION n The 10-bit LTC®1852 and 12-bit LTC1853 are complete 8-channel data acquisition systems. They include a ﬂexible 8-channel multiplexer, a 400ksps successive approximation analog-to-digital converter, an internal reference and a parallel output interface. The multiplexer can be conﬁgured for single-ended or differential inputs, two gain ranges and unipolar or bipolar operation.
PAGE 2
LTC1852/LTC1853 ABSOLUTE MAXIMUM RATINGS OVDD = VDD (Note 1, 2) Supply Voltage (VDD) ..................................................6V Analog Input Voltage (Note 3) ..... – 0.3V to (VDD + 0.3V) Digital Input Voltage (Note 4) .................... –0.3V to 10V Digital Output Voltage ..................–0.3V to (VDD + 0.3V) Power Dissipation ...............................................500mW Ambient Operating Temperature Range LTC1852C/LTC1853C ..............................
PAGE 3
LTC1852/LTC1853 CONVERTER CHARACTERISTICS The l denotes the speciﬁcations which apply over the full operating temperature range, otherwise speciﬁcations are at TA = 25°C. VDD = 2.7V to 5.5V, REFCOMP < VDD (Notes 5,6) PARAMETER CONDITIONS MIN l Resolution (No Missing Codes) Integral Linearity Error (Note 7) Differential Linearity Error Offset Error (Bipolar and Unipolar) Gain = 1 (PGA = 1) Gain = 2 (PGA = 0) (Note 8) REFCOMP ≥ 2V LTC1852 TYP 10 MAX UNITS Bits l ±0.25 ±1 ±0.35 ±1 LSB l ±0.
PAGE 4
LTC1852/LTC1853 INTERNAL REFERENCE TA = 25°C. (Notes 5, 6) PARAMETER CONDITIONS MIN TYP MAX UNITS REFOUT Output Voltage IOUT = 0 2.48 2.50 2.52 V REFOUT Output Temperature Coefﬁcient IOUT = 0 ±15 ppm/°C REFOUT Line Regulation 2.7 ≤ VDD ≤ 5.5, IOUT = 0 0.01 LSB/V Reference Buffer Gain REFCOMP Output Voltage External 2.5V Reference (VDD = 5V) Internal 2.5V Reference (VDD = 5V) REFCOMP Impedance Impedance to GND, REFIN = VDD 1.6368 1.6384 1.6400 V/V 4.092 4.060 4.096 4.096 4.
PAGE 5
LTC1852/LTC1853 POWER REQUIREMENTS The ● denotes the speciﬁcations which apply over the full operating temperature range, otherwise speciﬁcations are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VDD Analog Positive Supply Voltage (Note 10) ● 2.7 5.5 V OVDD Output Positive Supply Voltage (Note 10) ● 2.7 5.5 V IDD Positive Supply Current VDD = OVDD = 5V, fS = 400kHz VDD = OVDD = 2.7V, fS = 250kHz ● ● 2 0.83 3 1.
PAGE 6
LTC1852/LTC1853 TIMING CHARACTERISTICS The ● denotes the speciﬁcations which apply over the full operating temperature range, otherwise speciﬁcations are at TA = 25°C.
PAGE 7
LTC1852/LTC1853 PIN FUNCTIONS CH0 to CH7 (Pins 1 to 8): Analog Input Pins. Input pins can be used single ended relative to the analog input common pin or differentially in pairs (CH0 and CH1, CH2 and CH3, CH4 and CH5, CH6 and CH7). COM (Pin 9): Analog Input Common Pin. For single-ended operation (DIFF = 0), COM is the “–” analog input. COM is disabled when DIFF is high. REFOUT (Pin 10): Internal 2.5V Reference Output. Bypass to analog ground plane with 1μF.
PAGE 8
LTC1852/LTC1853 PIN FUNCTIONS D9/S0 (Pin 23, LTC1853): Three-State Digital Data Outputs. Active when RD is low. Following a conversion, bit 9 of the present conversion is available on this pin. In Readback mode, the end of sequence bit of the current sequencer location (S0) is available on this pin. The output swings between OVDD and OGND. D6 to D0 (Pins 24 to 30, LTC1852): Three-State Digital Data Outputs. Active when RD is low. The outputs swing between OVDD and OGND.
PAGE 9
LTC1852/LTC1853 PIN FUNCTIONS NOMINAL (V) TYP PIN NAME MAX 1 to 8 9 10 REFOUT 2.5V Reference Output 11 REFIN Reference Buffer Input 12 REFCOMP Reference Buffer Output 13 GND Ground 14 VDD Positive Supply 2.7 5 5.5 15 VDD Positive Supply 2.7 5 16 GND Ground 17 DIFFOUT/S6 Single-Ended/Differential Output 18 A2OUT/S5 19 20 ABSOLUTE MAXIMUM (M) MIN MAX DESCRIPTION MIN CH0 to CH7 Analog Inputs 0 VDD –0.3 VDD + 0.3 COM Analog Input Common Pin 0 VDD –0.3 VDD + 0.
PAGE 10
LTC1852/LTC1853 APPLICATIONS INFORMATION The LTC1852/LTC1853 are complete and very ﬂexible data acquisition systems. They consist of a 10-bit/12-bit, 400ksps capacitive successive approximation A/D converter with a wideband sample-and-hold, a conﬁgurable 8-channel analog input multiplexer, an internal reference and reference buffer ampliﬁer, a 16-bit parallel digital output and digital control logic, including a programmable sequencer.
PAGE 11
LTC1852/LTC1853 APPLICATIONS INFORMATION If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. For example, the 2nd order IMD terms include (fa ± fb).
PAGE 12
LTC1852/LTC1853 APPLICATIONS INFORMATION The LTC1852/LTC1853 have a unique differential sampleand-hold circuit that allows rail-to-rail inputs. The ADC will always convert the difference of the “+” and “–” inputs independent of the common mode voltage. The common mode rejection holds up to high frequencies. The only requirement is that both inputs can not exceed the AVDD power supply voltage or ground.
PAGE 13
LTC1852/LTC1853 APPLICATIONS INFORMATION LT1809/LT1810: Single and Dual 180MHz Rail-to-Rail Voltage Feedback Ampliﬁer. Single 3V to ±15V supplies. 20mA supply current. Lowest distortion. LT1812/LT1813: Single and Dual 100MHz Voltage Feedback Ampliﬁer. Single 5V to ±5V supplies. 3.6mA supply current. Low noise and low distortion. or DAC. If REFIN is tied low, the internal 2.5V reference divided by 2 (1.25V) is connected internally to the input of the reference buffer resulting in 2.048V on REFCOMP.
PAGE 14
LTC1852/LTC1853 APPLICATIONS INFORMATION adjusted until the output code ﬂickers between 1111 1111 1110 and 1111 1111 1111 for the LTC1853 and between 11 1111 1110 and 11 1111 1111 for the LTC1852. For bipolar inputs, an input voltage of FS – 1.5LSBs should be applied to the “+” input and the appropriate reference adjusted until the output code ﬂickers between 0111 1111 1110 and 0111 1111 1111 for the LTC1853 and between 01 1111 1110 and 01 1111 1111 for the LTC1852.
PAGE 15
LTC1852/LTC1853 APPLICATIONS INFORMATION BOARD LAYOUT AND BYPASSING To obtain the best performance from the LTC1852/LTC1853, a printed circuit board with ground plane is required. The ground plane under the ADC area should be as free of breaks and holes as possible, such that a low impedance path between all ADC grounds and all ADC decoupling capacitors is provided. It is critical to prevent digital noise from being coupled to the analog inputs, reference or analog power supply lines.
PAGE 16
LTC1852/LTC1853 APPLICATIONS INFORMATION the ADC has been selected (i.e., CS is low). Once initiated, it cannot be restarted until the conversion is complete. Converter status is indicated by the BUSY output. BUSY is low during a conversion. If CONVST returns high at a critical point during the conversion it can create small errors. For the best results, ensure that CONVST returns high either within 400ns after the start of the conversion or after BUSY rises. CS t2 CONVST t1 RD 18523 F04 Figure 4.
PAGE 17
LTC1852/LTC1853 APPLICATIONS INFORMATION t8 tCONV t5 t13 CONVST t6 t6 BUSY t7 DATA DATA (N – 1) DATA N 18523 F06 Figure 6. Mode 1b CONVST Starts a Conversion, RD = CS = 0 tCONV t5 t8 CONVST t13 t6 BUSY t9 t12 RD t10 DATA t11 DATA N 18523 F07 Figure 7. Mode 2 CONVST Starts a Conversion. Data is Read by RD, CS = 0 tCONV t8 RD = CONVST t11 t6 BUSY t10 DATA t7 DATA (N – 1) DATA N DATA N DATA (N + 1) 18523 F08 Figure 8.
PAGE 18
LTC1852/LTC1853 APPLICATIONS INFORMATION appear on the data outputs; BUSY goes high releasing the processor, and the processor takes RD ( = CONVST) back high and reads the new conversion data. In ROM mode, the processor takes RD ( = CONVST) low, starting a conversion and reading the previous conversion result. After the conversion is complete, the processor can read the new result and initiate another conversion.
PAGE 19
LTC1852/LTC1853 APPLICATIONS INFORMATION The sequencer is accessed by taking the M1 mode pin high. With M1 high, the sequencer memory is accessed by taking the M0 mode pin low. This will cause BUSY to go low, disabling conversions during the programming and readback of the sequencer. The sequencer is reset to location 0000 whenever M1 or M0 changes state.
PAGE 20
Hi-Z D6 TO D0 (LTC1852) D8 TO D0 (LTC1853) S6 TO S0 Hi-Z L0CATION 0001 L0CATION 0000 PGA BUSY L0CATION 0001 L0CATION 0000 UNI/BIP t19 L0CATION 0001 L0CATION 0000 A2 TO A0 t16 L0CATION 0001 t17 L0CATION 0000 t20 t18 DIFF RD WR CONVST M0 M1 t23 LOCATION 0000 t11 t24 Figure 11.
PAGE 21
Hi-Z DIFFOUT A2OUT TO A0OUT D9 TO D0 (LTC1852) D11 TO D0 (LTC1853) L0CATION 0010 L0CATION 0010 L0CATION 0010 L0CATION 0010 t23 t25 t6 CONVERT 0000 t8 DATA 0000 CONVERT 0001 Figure 12.
PAGE 22
LTC1852/LTC1853 TYPICAL APPLICATIONS LTC1853 Hardwired for 8-Channel Single-Ended Scan with Unipolar 0V to 4.096V Operation 5V 10μF 0.1μF 15 14 VDD VDD M1 48 M0 36 LTC1853 5V CS 46 1 CH0 CONVST 45 CONTROL LOGIC AND PROGRAMMABLE SEQUENCER 2 CH1 3 CH2 INPUT CONFIGURATION: ALL 8 CHANNELS SINGLE ENDED TO COM CH0–CH7: 0V TO 4.
PAGE 23
LTC1852/LTC1853 TYPICAL APPLICATIONS LTC1853 Hardwired for 4-Channel Differential Scan with Bipolar ±1.024V Operation 5V 10μF 14 0.1μF 15 VDD VDD M1 48 M0 36 LTC1853 + – + INPUT CONFIGURATION: 4 DIFFERENTIAL CHANNELS: ±1.
PAGE 24
LTC1852/LTC1853 TYPICAL APPLICATION Data buffering using two IDT7202LA15 1k x 9-bit FIFOs allows rapid collection of 1024 samples and simple interface to low power, low speed, 8-bit microcontrollers. Data and channel information are clocked in simultaneously and read out as two bytes using READ HIGH FIFO and READ LOW FIFO lines. In the event of bus contention, resistors limit peak output current.