Datasheet

ManualsBrandsLINEAR TECHNOLOGY ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal QFN 32

LTC2255/LTC2254

22554fa

FEATURES

DESCRIPTIO

APPLICATIO S

TYPICAL APPLICATIO

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Sample Rate: 125Msps/105Msps

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Single 3V Supply (2.85V to 3.4V)

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Low Power: 395mW/320mW

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72.4dB SNR

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88dB SFDR

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No Missing Codes

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Flexible Input: 1V

P-P

to 2V

P-P

Range

■

640MHz Full Power Bandwidth S/H

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Clock Duty Cycle Stabilizer

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Shutdown and Nap Modes

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Pin Compatible Family

125Msps: LTC2253 (12-Bit), LTC2255 (14-Bit)

105Msps: LTC2252 (12-Bit), LTC2254 (14-Bit)

80Msps: LTC2229 (12-Bit), LTC2249 (14-Bit)

65Msps: LTC2228 (12-Bit), LTC2248 (14-Bit)

40Msps: LTC2227 (12-Bit), LTC2247 (14-Bit)

25Msps: LTC2226 (12-Bit), LTC2246 (14-Bit)

10Msps: LTC2225 (12-Bit), LTC2245 (14-Bit)

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32-Pin (5mm × 5mm) QFN Package

14-Bit, 125/105Msps

Low Power 3V ADCs

The LTC

2255/LTC2254 are 14-bit 125Msps/105Msps,

low power 3V A/D converters designed for digitizing high

frequency, wide dynamic range signals. The LTC2255/

LTC2254 are perfect for demanding imaging and commu-

nications applications with AC performance that includes

72.3dB SNR and 85dB SFDR for signals at the Nyquist

frequency.

DC specs include ±1LSB INL (typ), ±0.5LSB DNL (typ) and

no missing codes over temperature. The transition noise

is a low 1.3 LSB

RMS

A single 3V supply allows low power operation. A separate

output supply allows the outputs to drive 0.5V to 3.3V

logic.

A single-ended CLK input controls converter operation. An

optional clock duty cycle stabilizer allows high perfor-

mance at full speed for a wide range of clock duty cycles.

LTC2255: SNR vs Input Frequency,

–1dB, 2V Range, 125Msps

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Wireless and Wired Broadband Communication

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Imaging Systems

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Ultrasound

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Spectral Analysis

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Portable Instrumentation

–

INPUT

S/H

CORRECTION

LOGIC

OUTPUT

DRIVERS

14-BIT

PIPELINED

ADC CORE

CLOCK/DUTY

CYCLE

CONTROL

FLEXIBLE

REFERENCE

D13

•

CLK

REFH

REFL

ANALOG

INPUT

22554 TA01a

OGND

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

INPUT FREQUENCY (MHz)

SNR (dBFS)

100

200

250

33554 G09

150

300

350

Summary of content (24 pages)

PAGE 1
LTC2255/LTC2254 14-Bit, 125/105Msps Low Power 3V ADCs U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO The LTC®2255/LTC2254 are 14-bit 125Msps/105Msps, low power 3V A/D converters designed for digitizing high frequency, wide dynamic range signals. The LTC2255/ LTC2254 are perfect for demanding imaging and communications applications with AC performance that includes 72.3dB SNR and 85dB SFDR for signals at the Nyquist frequency. Sample Rate: 125Msps/105Msps Single 3V Supply (2.85V to 3.
PAGE 2
LTC2255/LTC2254 U W U PACKAGE/ORDER I FOR ATIO ORDER PART NUMBER D11 D12 SENSE VCM TOP VIEW VDD Supply Voltage (VDD) ................................................. 4V Digital Output Ground Voltage (OGND) ....... –0.3V to 1V Analog Input Voltage (Note 3) ..... –0.3V to (VDD + 0.3V) Digital Input Voltage .................... –0.3V to (VDD + 0.3V) Digital Output Voltage ................ –0.3V to (OVDD + 0.3V) Power Dissipation ............................................
PAGE 3
LTC2255/LTC2254 U U A ALOG I PUT The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS VIN Analog Input Range (AIN+ –AIN–) 2.85V < VDD < 3.4V (Note 7) ● VIN,CM Analog Input Common Mode Differential Input (Note 7) ● 1 1.
PAGE 4
LTC2255/LTC2254 U U U I TER AL REFERE CE CHARACTERISTICS (Note 4) PARAMETER CONDITIONS MIN TYP MAX UNITS VCM Output Voltage IOUT = 0 1.475 1.500 1.525 V ±25 VCM Output Tempco ppm/°C VCM Line Regulation 2.85V < VDD < 3.4V 3 mV/V VCM Output Resistance –1mA < IOUT < 1mA 4 Ω U U DIGITAL I PUTS A D DIGITAL OUTPUTS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
PAGE 5
LTC2255/LTC2254 WU TI I G CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN fs Sampling Frequency (Note 9) ● 1 tL CLK Low Time Duty Cycle Stabilizer Off Duty Cycle Stabilizer On (Note 7) ● ● 3.8 3 tH CLK High Time Duty Cycle Stabilizer Off Duty Cycle Stabilizer On (Note 7) ● ● 3.
PAGE 6
LTC2255/LTC2254 U W TYPICAL PERFOR A CE CHARACTERISTICS LTC2255: Typical INL, 2V Range, 125Msps LTC2255: 8192 Point FFT, fIN = 5MHz, –1dB, 2V Range, 125Msps LTC2255: Typical DNL, 2V Range, 125Msps 2.0 1.5 1.0 0 0.8 –10 –20 0.6 0 –0.5 0.2 0 –0.2 –0.4 –1.0 –0.8 –2.0 –1.
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LTC2255/LTC2254 U W TYPICAL PERFOR A CE CHARACTERISTICS LTC2255: SNR and SFDR vs Sample Rate, 2V Range, fIN = 5MHz, –1dB LTC2255: SFDR vs Input Frequency, –1dB, 2V Range, 125Msps 100 80 90 SFDR 90 85 80 75 dBFS 70 80 SNR (dBc AND dBFS) SNR AND SFDR (dBFS) 95 SNR 70 60 60 50 dBc 40 30 20 70 10 0 –70 50 65 0 100 150 200 250 300 350 INPUT FREQUENCY (MHz) 22554 G10 20 40 60 80 100 120 140 160 22554 G11 SAMPLE RATE (Msps) LTC2255: SFDR vs Input Level, fIN = 70MHz, 2V Range, 125Msps –60 –
PAGE 8
LTC2255/LTC2254 U W TYPICAL PERFOR A CE CHARACTERISTICS LTC2254: Typical INL, 2V Range, 105Msps 2.0 1.5 1.0 0 0.8 –10 –20 0.6 1.0 0 –0.5 AMPLITUDE (dB) 0.5 –30 0.4 DNL ERROR (LSB) INL ERROR (LSB) LTC2254: 8192 Point FFT, fIN = 5MHz, –1dB, 2V Range, 105Msps LTC2254: Typical DNL, 2V Range, 105Msps 0.2 0 –0.2 –1.
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LTC2255/LTC2254 U W TYPICAL PERFOR A CE CHARACTERISTICS LTC2254: SNR and SFDR vs Sample Rate, 2V Range, fIN = 5MHz, –1dB LTC2254: SFDR vs Input Frequency, –1dB, 2V Range, 105Msps 100 80 90 SFDR 95 80 75 SNR (dBc AND dBFS) 85 dBFS 70 80 SNR AND SFDR (dBFS) 90 SNR 70 60 60 50 dBc 40 30 20 70 10 65 0 –70 50 100 150 200 250 300 350 INPUT FREQUENCY (MHz) 22554 G26 0 20 40 60 80 100 SAMPLE RATE (Msps) 120 140 –60 –50 –40 –30 –20 INPUT LEVEL (dBFS) 22554 G27 –10 0 22554 G28 LTC22
PAGE 10
LTC2255/LTC2254 U U U PI FU CTIO S AIN+ (Pin 1): Positive Differential Analog Input. AIN- (Pin 2): Negative Differential Analog Input. REFH (Pins 3, 4): ADC High Reference. Short together and bypass to pins 5, 6 with a 0.1µF ceramic chip capacitor as close to the pin as possible. Also bypass to pins 5, 6 with an additional 2.2µF ceramic chip capacitor and to ground with a 1µF ceramic chip capacitor. REFL (Pins 5, 6): ADC Low Reference. Short together and bypass to pins 3, 4 with a 0.
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LTC2255/LTC2254 W FUNCTIONAL BLOCK DIAGRA U U AIN+ AIN– VCM INPUT S/H FIRST PIPELINED ADC STAGE SECOND PIPELINED ADC STAGE THIRD PIPELINED ADC STAGE FOURTH PIPELINED ADC STAGE FIFTH PIPELINED ADC STAGE SIXTH PIPELINED ADC STAGE 1.5V REFERENCE SHIFT REGISTER AND CORRECTION 2.2µF RANGE SELECT REFH SENSE REFL INTERNAL CLOCK SIGNALS OVDD REF BUF OF D13 CLOCK/DUTY CYCLE CONTROL DIFF REF AMP CONTROL LOGIC OUTPUT DRIVERS • • • D0 REFH 22554 BD01 REFL 0.1µF OGND CLK M0DE SHDN OE 2.
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LTC2255/LTC2254 U W U U APPLICATIO S I FOR ATIO DYNAMIC PERFORMANCE input tone to the RMS value of the largest 3rd order intermodulation product. Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency.
PAGE 13
LTC2255/LTC2254 U W U U APPLICATIO S I FOR ATIO output by the residue amplifier. Successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. When CLK is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the “Input S/H” shown in the block diagram. At the instant that CLK transitions from low to high, the sampled input is held.
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LTC2255/LTC2254 U W U U APPLICATIO S I FOR ATIO Input Drive Impedance As with all high performance, high speed ADCs, the dynamic performance of the LTC2255/LTC2254 can be influenced by the input drive circuitry, particularly the second and third harmonics. Source impedance and reactance can influence SFDR. At the falling edge of CLK, the sample-and-hold circuit will connect the 3.5pF sampling capacitor to the input pin and start the sampling period.
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LTC2255/LTC2254 U W U U APPLICATIO S I FOR ATIO For input frequencies above 70MHz, the input circuits of Figure 6, 7 and 8 are recommended. The balun transformer gives better high frequency response than a flux coupled center tapped transformer. The coupling capacitors allow the analog inputs to be DC biased at 1.5V. In Figure 8, the series inductors are impedance matching elements that maximize the ADC bandwidth. VCM 2.2µF 0.1µF 12Ω ANALOG INPUT 25Ω 0.1µF T1 0.
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LTC2255/LTC2254 U W U U APPLICATIO S I FOR ATIO pins are needed to reduce package inductance. Bypass capacitors must be connected as shown in Figure 9. Other voltage ranges in-between the pin selectable ranges can be programmed with two external resistors as shown in Figure 10. An external reference can be used by applying its output directly or through a resistor divider to SENSE. It is not recommended to drive the SENSE pin with a logic device.
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LTC2255/LTC2254 U W U U APPLICATIO S I FOR ATIO bearing on how much SNR degradation will be experienced. For high crest factor signals such as WCDMA or OFDM, where the nominal power level must be at least 6dB to 8dB below full scale, the use of these translators will have a lesser impact. The transformer in the example may be terminated with the appropriate termination for the signaling in use.
PAGE 18
LTC2255/LTC2254 U W U U APPLICATIO S I FOR ATIO circuitry and may eliminate the need for external damping resistors. to 1V and must be less than OVDD. The logic outputs will swing between OGND and OVDD. As with all high speed/high resolution converters, the digital output loading can affect the performance. The digital outputs of the LTC2255/LTC2254 should drive a minimal capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry.
PAGE 19
LTC2255/LTC2254 U W U U APPLICATIO S I FOR ATIO further away. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. The LTC2255/LTC2254 differential inputs should run parallel and close to each other. The input traces should be as short as possible to minimize capacitance and to minimize noise pickup.
PAGE 20
J3 CLOCK INPUT R8 49.9Ω C12 0.1µF VDD E1 EXT REF VCM VDD R9 1k NC7SVU04 VCM 4 2 EXT 5 REF 6 3 1 VDD JP3 SENSE 4 • C19 0.1µF R10 33Ω VDD GND R16 1k R15 1k R14 1k VDD 1/3VDD 2/3VDD VDD 6 4 2 GND C15 2.2µF VDD 7 GND 8 5 3 1 C8 0.1µF C2 8.2pF C11 0.1µF VDD JP4 MODE JP2 OE C7 2.2µF R6 12.4Ω VDD C4 0.1µF R4 24.9Ω R3 24.9Ω R2 12.4Ω C14 0.1µF VCM VDD VDD C9 1µF C6 1µF JP1 SHDN R5 50Ω •3 2 T1 ETC1-1T 5 1 C13 0.1µF C3 0.1µF VCM C1 0.1µF C10 0.
PAGE 21
LTC2255/LTC2254 U W U U APPLICATIO S I FOR ATIO Silkscreen Top Topside Inner Layer 2 GND 22554fa 21
PAGE 22
LTC2255/LTC2254 U W U U APPLICATIO S I FOR ATIO Inner Layer 3 Power Bottomside Silkscreen Bottom 22554fa 22
PAGE 23
LTC2255/LTC2254 U PACKAGE DESCRIPTIO UH Package 32-Lead Plastic QFN (5mm × 5mm) (Reference LTC DWG # 05-08-1693) 0.70 ±0.05 5.50 ±0.05 4.10 ±0.05 3.45 ±0.05 (4 SIDES) PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC RECOMMENDED SOLDER PAD LAYOUT 5.00 ± 0.10 (4 SIDES) BOTTOM VIEW—EXPOSED PAD PIN 1 NOTCH R = 0.30 TYP OR 0.35 × 45° CHAMFER R = 0.115 TYP 0.75 ± 0.05 0.00 – 0.05 31 32 0.40 ± 0.10 PIN 1 TOP MARK (NOTE 6) 1 2 3.45 ± 0.10 (4-SIDES) (UH32) QFN 1004 0.200 REF NOTE: 1.
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LTC2255/LTC2254 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1747 12-Bit, 80Msps ADC 72dB SNR, 87dB SFDR, 48-Pin TSSOP Package LTC1748 14-Bit, 80Msps ADC 76.3dB SNR, 90dB SFDR, 48-Pin TSSOP Package LTC1749 12-Bit, 80Msps Wideband ADC Up to 500MHz IF Undersampling, 87dB SFDR LTC1750 14-Bit, 80Msps Wideband ADC Up to 500MHz IF Undersampling, 90dB SFDR LT1993 High Speed Differential Op Amp 600MHz BW, 75dBc Distortion at 70MHz LTC2220 12-Bit, 170Msps ADC 890mW, 67.