LTC2265-14/ LTC2264-14/LTC2263-14 14-Bit, 65Msps/40Msps/ 25Msps Low Power Dual ADCs FEATURES n n n n n n n n n n n n n DESCRIPTION 2-Channel Simultaneous Sampling ADC 73.7dB SNR 90dB SFDR Low Power: 171mW/113mW/94mW Total 85mW/56mW/47mW per Channel Single 1.
LTC2265-14/ LTC2264-14/LTC2263-14 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Notes 1 and 2) OUT1A– OUT1A+ GND SDO PAR/SER VREF GND SENSE VDD TOP VIEW VDD Supply Voltages VDD, OVDD................................................. –0.3V to 2V Analog Input Voltage (AIN +, AIN –, PAR/SER, SENSE) (Note 3)......................................... –0.3V to (VDD + 0.2V) Digital Input Voltage (ENC+, ENC–, CS, SDI, SCK) (Note 4)...................................................... –0.3V to 3.
LTC2265-14/ LTC2264-14/LTC2263-14 CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) LTC2265-14 PARAMETER CONDITIONS MIN LTC2264-14 TYP MAX MIN LTC2263-14 TYP MAX TYP MAX UNITS l 14 Integral Linearity Error Differential Analog Input (Note 6) l –3 ±1 3 –3 ±1 3 –3 ±1 3 LSB Differential Linearity Error Differential Analog Input l –0.8 ±0.3 0.8 –0.8 ±0.3 0.8 –0.
LTC2265-14/ LTC2264-14/LTC2263-14 DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS.
LTC2265-14/ LTC2264-14/LTC2263-14 DIGITAL INPUTS AND OUTPUTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Single-Ended Encode Mode (ENC– Tied to GND) VIH High Level Input Voltage VDD = 1.8V l VIL Low Level Input Voltage VDD = 1.8V l VIN Input Voltage Range ENC+ to GND l RIN Input Resistance (See Figure 11) CIN Input Capacitance 1.2 V 0 0.
LTC2265-14/ LTC2264-14/LTC2263-14 TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER Sampling Frequency fS ENC Low Time (Note 8) tENCL tENCH ENC High Time (Note 8) tAP Sample-and-Hold Acquisition Delay Time SYMBOL PARAMETER CONDITIONS (Notes 10, 11) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On Duty Cycle Stabilizer Off Duty Cycle Stabilizer On l l l l l MIN 5 7.
LTC2265-14/ LTC2264-14/LTC2263-14 TIMING DIAGRAMS 2-Lane Output Mode, 16-Bit Serialization* tAP ANALOG INPUT N+1 N tENCH tENCL ENC– ENC+ tSER DCO– DCO+ tDATA tFRAME FR– FR+ tSER tPD tSER – OUT#A OUT#A+ OUT#B– OUT#B+ D5 D3 D1 0 D13 D11 D9 D7 D5 D3 D1 0 D13 D11 D9 D4 D2 D0 0 D12 D10 D8 D6 D4 D2 D0 0 D12 D10 D8 SAMPLE N-6 SAMPLE N-5 226514 TD01 SAMPLE N-4 *SEE THE DIGITAL OUTPUTS SECTION 2-Lane Output Mode, 14-Bit Serialization tAP ANALOG INPUT N+2 N+1 N tEN
LTC2265-14/ LTC2264-14/LTC2263-14 TIMING DIAGRAMS 2-Lane Output Mode, 12-Bit Serialization tAP ANALOG INPUT N+1 N tENCH tENCL ENC– ENC+ tSER DCO– DCO+ tDATA tFRAME FR+ FR– tPD tSER – OUT#A OUT#A+ OUT#B– OUT#B+ tSER D9 D7 D5 D3 D13 D11 D9 D7 D5 D3 D13 D11 D9 D8 D6 D4 D2 D12 D10 D8 D6 D4 D2 D12 D10 D8 SAMPLE N-6 SAMPLE N-5 226514 TD03 SAMPLE N-4 1-Lane Output Mode, 16-Bit Serialization tAP ANALOG INPUT N+1 N tENCH tENCL ENC– ENC+ tSER DCO– DCO+ tFRAME FR–
LTC2265-14/ LTC2264-14/LTC2263-14 TIMING DIAGRAMS 1-Lane Output Mode, 14-Bit Serialization tAP ANALOG INPUT N+1 N tENCH tENCL ENC– ENC+ tSER DCO– DCO+ tFRAME FR– FR+ OUT#A– OUT#A+ tDATA tSER tPD D3 D2 D1 tSER D0 D13 SAMPLE N-6 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D13 SAMPLE N-5 D12 D11 D10 226514 TD05 SAMPLE N-4 OUT#B+, OUT#B– ARE DISABLED 1-Lane Output Mode, 12-Bit Serialization tAP ANALOG INPUT N+1 N tENCH tENCL ENC– ENC+ tSER DCO– DCO+ tFRAME FR– FR+ OUT#
LTC2265-14/ LTC2264-14/LTC2263-14 TYPICAL PERFORMANCE CHARACTERISTICS LTC2265-14: Integral Nonlinearity (INL) LTC2265-14: Differential Nonlinearity (DNL) 2.0 1.5 0 0.8 –10 –20 0.5 0 –0.5 –1.0 –30 0.4 AMPLITUDE (dBFS) DNL ERROR (LSB) INL ERROR (LSB) 1.0 0.6 1.0 0.2 0 –0.2 –0.4 –0.8 0 4096 8192 12288 OUTPUT CODE –1.
LTC2265-14/ LTC2264-14/LTC2263-14 TYPICAL PERFORMANCE CHARACTERISTICS LTC2265-14: SFDR vs Input Frequency, –1dBFS, 2V Range, 65Msps LTC2265-14: SFDR vs Input Level, fIN = 70MHz, 2V Range, 65Msps 95 100 dBFS SFDR (dBc AND dBFS) 90 85 80 75 80 70 60 dBc 50 60 40 30 40 30 20 10 10 65 0 50 100 150 200 250 300 INPUT FREQUENCY (MHz) 0 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 350 dBc 50 20 70 dBFS 70 SNR (dBc AND dBFS) 90 SFDR (dBFS) 80 110 LTC2265-14: SNR vs Input Level, fI
LTC2265-14/ LTC2264-14/LTC2263-14 TYPICAL PERFORMANCE CHARACTERISTICS 0 LTC2264-14: 8k Point FFT, fIN = 69MHz, –1dBFS, 40Msps 0 –10 –10 –10 –20 –20 –20 –30 –30 –40 –50 –60 –70 –80 –40 –50 –60 –70 –80 –40 –50 –60 –70 –80 –90 –100 –90 –100 –90 –100 –110 –120 –110 –120 –110 –120 0 20 10 FREQUENCY (MHz) 0 20 10 FREQUENCY (MHz) 226514 G19 226514 G21 LTC2264-14: Shorted Input Histogram 0 74 6000 –20 73 5000 72 –30 –40 –50 –60 –70 SNR (dBFS) 4000 COUNT 3000 –80 2000 –90 –1
LTC2265-14/ LTC2264-14/LTC2263-14 TYPICAL PERFORMANCE CHARACTERISTICS LTC2264-14: SNR vs SENSE, fIN = 5MHz, –1dBFS 1.5 72 1.0 INL ERROR (LSB) 73 SNR (dBFS) 71 70 69 –0.5 67 –1.5 66 –2.0 0.8 0.9 1 1.1 SENSE PIN (V) 1.2 1.3 0.6 0 –1.0 0.7 0.8 0.5 68 0.6 1.0 2.0 DNL ERROR (LSB) 74 0.2 0 –0.2 –0.4 –0.8 0 4096 8192 12288 OUTPUT CODE –1.
LTC2265-14/ LTC2264-14/LTC2263-14 TYPICAL PERFORMANCE CHARACTERISTICS LTC2263-14: SNR vs Input Frequency, –1dBFS, 2V Range, 25Msps LTC2263-14: SFDR vs Input Frequency, –1dBFS, 2V Range, 25Msps 110 95 74 100 73 90 70 69 SFDR (dBc AND dBFS) SFDR (dBFS) SNR (dBFS) 71 85 80 75 68 0 100 150 200 250 300 INPUT FREQUENCY (MHz) 50 350 dBc 60 50 40 30 0 50 100 150 200 250 300 INPUT FREQUENCY (MHz) DCO Cycle-Cycle Jitter vs Serial Data Rate 74 350 73 300 PEAK-TO-PEAK JITTER (ps) 45 SNR (dBF
LTC2265-14/ LTC2264-14/LTC2263-14 PIN FUNCTIONS AIN1+ (Pin 1): Channel 1 Positive Differential Analog Input. AIN1– (Pin 2): Channel 1 Negative Differential Analog Input. VCM1 (Pin 3): Common Mode Bias Output, Nominally Equal to VDD /2. VCM should be used to bias the common mode of the analog inputs of channel 1. Bypass to ground with a 0.1µF ceramic capacitor. REFH (Pins 4, 5): ADC High Reference. Bypass to pins 6, 7 with a 2.2µF ceramic capacitor, and to ground with a 0.1µF ceramic capacitor.
LTC2265-14/ LTC2264-14/LTC2263-14 PIN FUNCTIONS LVDS OUTPUTS PAR/SER (Pin 35): Programming Mode Selection Pin. Connect to ground to enable the serial programming mode. CS, SCK, SDI and SDO become a serial interface that controls the A/D operating modes. Connect to VDD to enable parallel programming mode where CS, SCK, SDI and SDO become parallel logic inputs that control a reduced set of the A/D operating modes.
LTC2265-14/ LTC2264-14/LTC2263-14 FUNCTIONAL BLOCK DIAGRAM ENC+ ENC– 1.8V 1.8V VDD CHANNEL 1 ANALOG INPUT OVDD 14-BIT ADC CORE SAMPLEAND-HOLD PLL OUT1A OUT1B CHANNEL 2 ANALOG INPUT DATA SERIALIZER 14-BIT ADC CORE SAMPLEAND-HOLD OUT2A OUT2B VREF 1µF 1.25V REFERENCE DATA CLOCKOUT FRAME RANGE SELECT REFH REF BUF SENSE REFL OGND VDD /2 DIFF REF AMP 226514 F01 MODE CONTROL REGISTERS GND REFH 0.1µF REFL VCM1 0.1µF VCM2 0.1µF PAR/SER CS SCK SDI SDO 2.2µF 0.1µF 0.1µF Figure 1.
LTC2265-14/ LTC2264-14/LTC2263-14 APPLICATIONS INFORMATION CONVERTER OPERATION Transformer Coupled Circuits The LTC2265-14/LTC2264-14/LTC2263-14 are low power, 2-channel, 14-bit, 65Msps/40Msps/25Msps A/D converters that are powered by a single 1.8V supply. The analog inputs should be driven differentially. The encode input can be driven differentially for optimal jitter performance, or single-ended for lower power consumption. To minimize the number of data lines, the digital outputs are serial LVDS.
LTC2265-14/ LTC2264-14/LTC2263-14 APPLICATIONS INFORMATION Amplifier Circuits Figure 7 shows the analog input being driven by a high speed differential amplifier. The output of the amplifier is ACcoupled to the A/D so the amplifier’s output common mode voltage can be optimally set to minimize distortion. 50Ω At very high frequencies an RF gain block will often have lower distortion than a differential amplifier.
LTC2265-14/ LTC2264-14/LTC2263-14 APPLICATIONS INFORMATION Reference Encode Input The LTC2265-14/LTC2264-14/LTC2263-14 has an internal 1.25V voltage reference. For a 2V input range using the internal reference, connect SENSE to VDD. For a 1V input range using the internal reference, connect SENSE to ground. For a 2V input range with an external reference, apply a 1.25V reference voltage to SENSE (Figure 9). The signal quality of the encode inputs strongly affects the A/D noise performance.
LTC2265-14/ LTC2264-14/LTC2263-14 APPLICATIONS INFORMATION The differential encode mode is recommended for sinusoidal, PECL, or LVDS encode inputs (Figures 12 and 13). The encode inputs are internally biased to 1.2V through 10k equivalent resistance. The encode inputs can be taken above VDD (up to 3.6V), and the common mode range is from 1.1V to 1.6V. In the differential encode mode, ENC – should stay at least 200mV above ground to avoid falsely triggering the single-ended encode mode.
LTC2265-14/ LTC2264-14/LTC2263-14 APPLICATIONS INFORMATION Table 1. Maximum Sampling Frequency for All Serialization Modes. Note That These Limits Are for the LTC2265-14. The Sampling Frequency for the Slower Speed Grades Cannot Exceed 40MHz (LTC2264-14) or 25MHz (LTC2263-14). MAXIMUM SAMPLING FREQUENCY, fS (MHz) SERIALIZATION MODE DCO FREQUENCY FR FREQUENCY SERIAL DATA RATE 2-Lane 16-Bit Serialization 65 4 • fS fS 8 • fS 2-Lane 14-Bit Serialization 65 3.5 • fS 0.
LTC2265-14/ LTC2264-14/LTC2263-14 APPLICATIONS INFORMATION The digital output is randomized by applying an exclusive-OR logic operation between the LSB and all other data output bits. To decode, the reverse operation is applied—an exclusive-OR operation is applied between the LSB and all other bits. The FR and DCO outputs are not affected. The output randomizer is enabled by serially programming mode control register A1.
LTC2265-14/ LTC2264-14/LTC2263-14 APPLICATIONS INFORMATION Serial data transfer starts when CS is taken low. The data on the SDI pin is latched at the first 16 rising edges of SCK. Any SCK rising edges after the first 16 are ignored. The data transfer ends when CS is taken high again. The first bit of the 16-bit input word is the R/W bit. The next seven bits are the address of the register (A6:A0). The final eight bits are the register data (D7:D0).
LTC2265-14/ LTC2264-14/LTC2263-14 APPLICATIONS INFORMATION REGISTER A2: OUTPUT MODE REGISTER (ADDRESS 02h) D7 D6 D5 D4 D3 D2 D1 D0 ILVDS2 ILVDS1 ILVDS0 TERMON OUTOFF OUTMODE2 OUTMODE1 OUTMODE0 Bits 7-5 ILVDS2: ILVDS0 LVDS Output Current Bits 000 = 3.5mA LVDS Output Driver Current 001 = 4.0mA LVDS Output Driver Current 010 = 4.5mA LVDS Output Driver Current 011 = Not Used 100 = 3.0mA LVDS Output Driver Current 101 = 2.5mA LVDS Output Driver Current 110 = 2.
LTC2265-14/ LTC2264-14/LTC2263-14 APPLICATIONS INFORMATION GROUNDING AND BYPASSING The LTC2265-14/LTC2264-14/LTC2263-14 requires a printed circuit board with a clean unbroken ground plane. A multilayer board with an internal ground plane in the first layer beneath the ADC is recommended. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible.
LTC2265-14/ LTC2264-14/LTC2263-14 TYPICAL APPLICATIONS Silkscreen Top Top Side Inner Layer 2 GND Inner Layer 3 22654314fb 27
LTC2265-14/ LTC2264-14/LTC2263-14 TYPICAL APPLICATIONS Inner Layer 4 Inner Layer 5 Power Bottom Side Silkscreen Bottom 22654314fb 28
LTC2265-14/ LTC2264-14/LTC2263-14 TYPICAL APPLICATIONS LTC2265 Schematic PAR/SER C4 1µF SDO SENSE VDD C5 1µF 9 10 OUT1A– OUT1A+ SDO GND PAR/SER GND VREF 28 REFH DCO– 27 LTC2265 REFH OVDD 26 25 REFL OGND REFL FR+ VCM2 FR– AIN2+ OUT2A+ 22 AIN2– OUT2A– 21 VDD AIN2 AIN2 OUT2B+ C59 0.1µF DCO+ OUT2B– 8 VCM1 GND 7 29 SDI 6 OUT1B– SCK C3 0.1µF C30 0.1µF AIN1– CS C2 0.1µF C1 2.2µF 5 30 ENC– 3 4 DIGITAL OUTPUTS OUT1B+ AIN1+ ENC+ 2 VDD VDD 1 VDD C29 0.
LTC2265-14/ LTC2264-14/LTC2263-14 PACKAGE DESCRIPTION UJ Package 40-Lead (6mm × 6mm) Plastic QFN (Reference LTC DWG # 05-08-1728) 0.70 ± 0.05 6.50 ± 0.05 5.10 ± 0.05 4.42 ± 0.05 4.50 ± 0.05 (4 SIDES) 4.42 ± 0.05 PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 6.00 ± 0.10 (4 SIDES) 0.75 ± 0.05 R = 0.10 TYP R = 0.115 TYP 39 40 0.40 ± 0.10 PIN 1 TOP MARK (SEE NOTE 6) 1 4.50 REF (4-SIDES) 4.42 ± 0.
LTC2265-14/ LTC2264-14/LTC2263-14 REVISION HISTORY REV DATE DESCRIPTION PAGE NUMBER A 04/10 Revised Max Value for LTC2264-14 Sampling Frequency in Timing Characteristics 6 Revised Descriptions and Comments in Related Parts Section 32 B 07/11 Revised Software Reset paragraph and Table 4 in Applications Information section. 24 22654314fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use.
LTC2265-14/ LTC2264-14/LTC2263-14 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS ADCs LTC2170-14/LTC2171-14/ 14-Bit, 25Msps/40Msps/65Msps LTC2172-14 1.8V Quad ADCs, Ultralow Power 162mW/202mW/311mW, 73.7dB SNR, 90dB SFDR, Serial LVDS Outputs, 7mm × 8mm QFN-52 LTC2170-12/LTC2171-12/ 12-Bit, 25Msps/40Msps/65Msps LTC2172-12 1.8V Quad ADCs, Ultralow Power 160mW/198mW/306mW, 71dB SNR, 90dB SFDR, Serial LVDS Outputs, 7mm × 8mm QFN-52 LTC2173-12/LTC2174-12/ 12-Bit, 80Msps/105Msps/125Msps LTC2175-12 1.
