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LTC2265-12/

LTC2264-12/LTC2263-12

22654312fb

TYPICAL APPLICATION

DESCRIPTION

12-Bit, 65Msps/40Msps/

25Msps Low Power Dual ADCs

The LTC

2265-12/LTC2264-12/LTC2263-12 are 2-channel,

simultaneous sampling 12-bit A/D converters designed for

digitizing high frequency, wide dynamic range signals. They

are perfect for demanding communications applications

with AC performance that includes 71dB SNR and 90dB

spurious free dynamic range (SFDR). Ultralow jitter of

0.15ps

RMS

allows undersampling of IF frequencies with

excellent noise performance.

DC specs include ±0.3LSB INL (typ), ±0.1LSB DNL (typ)

and no missing codes over temperature. The transition

noise is a low 0.3LSB

RMS

The digital outputs are serial LVDS to minimize the num-

ber of data lines. Each channel outputs two bits at a time

(2-lane mode) or one bit at a time (1-lane mode). The LVDS

drivers have optional internal termination and adjustable

output levels to ensure clean signal integrity.

The ENC

and ENC

–

inputs may be driven differentially

or single-ended with a sine wave, PECL, LVDS, TTL, or

CMOS inputs. An internal clock duty cycle stabilizer

allows high performance at full speed for a wide range of

clock duty cycles.

LTC2265-12, 65Msps,

2-Tone FFT, f

= 70MHz and 75MHz

FEATURES

APPLICATIONS

2-Channel Simultaneous Sampling ADC

71dB SNR

90dB SFDR

Low Power: 167mW/112mW/94mW Total

83mW/56mW/47mW per Channel

Single 1.8V Supply

Serial LVDS Outputs: 1 or 2 Bits per Channel

Selectable Input Ranges: 1V

P-P

to 2V

P-P

800MHz Full Power Bandwidth S/H

Shutdown and Nap Modes

Serial SPI Port for Conﬁguration

Pin Compatible 14-Bit and 12-Bit Versions

40-Pin (6mm × 6mm) QFN Package

Communications

Cellular Base Stations

Software Deﬁned Radios

Portable Medical Imaging

Multichannel Data Acquisition

Nondestructive Testing

CH.1

ANALOG

INPUT

CH.2

ANALOG

INPUT

ENCODE

INPUT

226512 TA01

GND OGND

–

S/H

–

S/H

12-BIT

ADC CORE

12-BIT

ADC CORE

PLL

DATA

SERIALIZER

SERIALIZED

LVDS

OUTPUTS

1.8V 1.8V

OUT1A

OUT1B

OUT2A

OUT2B

DATA

CLOCK

OUT

FRAME

FREQUENCY (MHz)

–100

–110

–120

–70

–60

–80

–90

AMPLITUDE (dBFS)

–50

–30

–40

–20

–10

20 30

226512 TA02

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

Summary of content (34 pages)

PAGE 1
LTC2265-12/ LTC2264-12/LTC2263-12 12-Bit, 65Msps/40Msps/ 25Msps Low Power Dual ADCs FEATURES n n n n n n n n n n n n n DESCRIPTION 2-Channel Simultaneous Sampling ADC 71dB SNR 90dB SFDR Low Power: 167mW/112mW/94mW Total 83mW/56mW/47mW per Channel Single 1.
PAGE 2
LTC2265-12/ LTC2264-12/LTC2263-12 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Notes 1 and 2) OUT1A– OUT1A+ GND SDO PAR/SER VREF GND SENSE VDD TOP VIEW VDD Supply Voltages VDD, OVDD................................................. –0.3V to 2V Analog Input Voltage (AIN +, AIN –, PAR/SER, SENSE) (Note 3)........................... –0.3V to (VDD + 0.2V) Digital Input Voltage (ENC+, ENC–, CS, SDI, SCK) (Note 4)..................................... –0.3V to 3.9V SDO (Note 4)..........................
PAGE 3
LTC2265-12/ LTC2264-12/LTC2263-12 CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) LTC2265-12 PARAMETER CONDITIONS MIN LTC2264-12 TYP MAX MIN LTC2263-12 TYP MAX TYP MAX UNITS l 12 Integral Linearity Error Differential Analog Input (Note 6) l –1 ±0.3 1 –1 ±0.3 1 –1 ±0.3 1 LSB Differential Linearity Error Differential Analog Input l –0.5 ±0.1 0.5 –0.4 ±0.1 0.
PAGE 4
LTC2265-12/ LTC2264-12/LTC2263-12 DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS.
PAGE 5
LTC2265-12/ LTC2264-12/LTC2263-12 DIGITAL INPUTS AND OUTPUTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS ENCODE INPUTS (ENC+, ENC– ) Differential Encode Mode (ENC– Not Tied to GND) VID Differential Input Voltage (Note 8) l 0.2 VICM Common Mode Input Voltage Internally Set Externally Set (Note 8) l 1.1 l 0.
PAGE 6
LTC2265-12/ LTC2264-12/LTC2263-12 POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) LTC2265-12 SYMBOL PARAMETER CONDITIONS LTC2264-12 LTC2263-12 MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS VDD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V OVDD Output Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.
PAGE 7
LTC2265-12/ LTC2264-12/LTC2263-12 TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
PAGE 8
LTC2265-12/ LTC2264-12/LTC2263-12 TIMING DIAGRAMS 2-Lane Output Mode, 16-Bit Serialization tAP ANALOG INPUT N+1 N tENCH tENCL ENC– ENC+ tSER DCO– DCO+ tDATA tFRAME FR– FR+ tSER tPD tSER – OUT#A OUT#A+ OUT#B– OUT#B+ D3 D1 DX* 0 D11 D9 D7 D5 D3 D1 DX* 0 D11 D9 D7 D2 D0 DY* 0 D10 D8 D6 D4 D2 D0 DY* 0 D10 D8 D6 SAMPLE N-6 SAMPLE N-5 226512 TD01 SAMPLE N-4 *DX AND DY ARE EXTRA NON-DATA BITS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14-BIT VERSIONS OF THESE A/Ds
PAGE 9
LTC2265-12/ LTC2264-12/LTC2263-12 TIMING DIAGRAMS 2-Lane Output Mode, 12-Bit Serialization tAP ANALOG INPUT N+1 N tENCH tENCL ENC– ENC+ tSER DCO– DCO+ tDATA tFRAME FR+ FR– tPD tSER OUT#A– OUT#A+ OUT#B– OUT#B+ tSER D7 D5 D3 D1 D11 D9 D7 D5 D3 D1 D11 D9 D7 D6 D4 D2 D0 D10 D8 D6 D4 D2 D0 D10 D8 D6 SAMPLE N-6 SAMPLE N-5 226512 TD03 SAMPLE N-4 1-Lane Output Mode, 16-Bit Serialization tAP ANALOG INPUT N+1 N tENCH tENCL ENC– ENC+ tSER DCO– DCO+ tFRAME FR– FR+ tD
PAGE 10
LTC2265-12/ LTC2264-12/LTC2263-12 TIMING DIAGRAMS 1-Lane Output Mode, 14-Bit Serialization tAP ANALOG INPUT N+1 N tENCH tENCL ENC– ENC+ tSER DCO– DCO+ tFRAME FR– FR+ OUT#A– OUT#A+ tDATA tSER tPD D1 D0 DX* tSER DY* D11 SAMPLE N-6 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DX* DY* SAMPLE N-5 D11 D10 D9 SAMPLE N-4 D8 226512 TD05 OUT#B+, OUT#B– ARE DISABLED *DX AND DY ARE EXTRA NON-DATA BITS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14-BIT VERSIONS OF THESE A/Ds.
PAGE 11
LTC2265-12/ LTC2264-12/LTC2263-12 TIMING DIAGRAMS SPI Port Timing (Readback Mode) tDS tS tDH tSCK tH CS SCK tDO SDI SDO R/W A6 A5 A4 A3 A2 A1 A0 XX D7 HIGH IMPEDANCE XX D6 XX D5 XX D4 XX D3 XX D2 XX XX D1 D0 SPI Port Timing (Write Mode) CS SCK SDI SDO R/W HIGH IMPEDANCE A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 226512 TD07 22654312fb 11
PAGE 12
LTC2265-12/ LTC2264-12/LTC2263-12 TYPICAL PERFORMANCE CHARACTERISTICS LTC2265-12: Differential Nonlinearity (DNL) 1.0 0 0.8 0.8 –10 0.6 0.6 0.4 0.4 0 –0.2 –0.4 0.2 0 –0.2 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 –1.0 0 1024 2048 3072 OUTPUT CODE 4096 –30 AMPLITUDE (dBFS) 0.
PAGE 13
LTC2265-12/ LTC2264-12/LTC2263-12 TYPICAL PERFORMANCE CHARACTERISTICS LTC2265-12: SFDR vs Input Frequency, –1dBFS, 2V Range, 65Msps LTC2265-12: SFDR vs Input Level, fIN = 70MHz, 2V Range, 65Msps 95 SFDR (dBc AND dBFS) 90 85 80 75 80 70 dBc 60 60 50 40 30 50 30 20 10 10 0 50 100 150 200 250 300 INPUT FREQUENCY (MHz) 0 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 350 226512 G10 71 1-LANE, 3.5mA IOVDD (mA) 20 70 0 72 2-LANE, 3.5mA 80 70 2-LANE, 1.75mA 10 69 68 1-LANE, 1.
PAGE 14
LTC2265-12/ LTC2264-12/LTC2263-12 TYPICAL PERFORMANCE CHARACTERISTICS 0 LTC2264-12: 8k Point FFT, fIN = 69MHz, –1dBFS, 40Msps 0 –10 –10 –20 –20 –20 –30 –30 –30 –40 –50 –60 –70 –80 AMPLITUDE (dBFS) –10 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 0 LTC2264-12: 8k Point FFT, fIN = 29MHz, –1dBFS, 40Msps –40 –50 –60 –70 –80 –40 –50 –60 –70 –80 –90 –100 –90 –100 –90 –100 –110 –120 –110 –120 –110 –120 0 20 10 FREQUENCY (MHz) 0 226512 G19 0 14000 –40 12000 –60 –70 71 70 SNR (dBFS) –30 CO
PAGE 15
LTC2265-12/ LTC2264-12/LTC2263-12 TYPICAL PERFORMANCE CHARACTERISTICS LTC2264-12: SNR vs SENSE, fIN = 5MHz, –1dBFS INL ERROR (LSB) 71 SNR (dBFS) 70 69 68 67 66 0.6 0.7 0.8 0.9 1 1.1 SENSE PIN (V) 1.2 1.0 1.0 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0 –0.2 –0.4 –0.2 –0.4 –0.6 –0.8 0 1024 2048 3072 OUTPUT CODE –1.
PAGE 16
LTC2265-12/ LTC2264-12/LTC2263-12 TYPICAL PERFORMANCE CHARACTERISTICS LTC2263-12: SNR vs Input Frequency, –1dBFS, 2V Range, 25Msps LTC2263-12: SFDR vs Input Frequency, –1dBFS, 2V Range, 25Msps 72 95 71 90 70 85 110 LTC2263-12: SFDR vs Input Level, fIN = 70MHz, 2V Range, 25Msps 69 68 80 75 67 70 66 65 dBFS 90 SFDR (dBc AND dBFS) SFDR (dBFS) SNR (dBFS) 100 80 70 dBc 60 50 40 30 20 10 0 100 150 200 250 300 INPUT FREQUENCY (MHz) 50 350 0 50 100 150 200 250 300 INPUT FREQUENCY (MHz)
PAGE 17
LTC2265-12/ LTC2264-12/LTC2263-12 PIN FUNCTIONS AIN1+ (Pin 1): Channel 1 Positive Differential Analog Input. AIN1– (Pin 2): Channel 1 Negative Differential Analog Input. VCM1 (Pin 3): Common Mode Bias Output, Nominally Equal to VDD /2. VCM should be used to bias the common mode of the analog inputs of channel 1. Bypass to ground with a 0.1µF ceramic capacitor. REFH (Pins 4, 5): ADC High Reference. Bypass to pins 6, 7 with a 2.2µF ceramic capacitor, and to ground with a 0.1µF ceramic capacitor.
PAGE 18
LTC2265-12/ LTC2264-12/LTC2263-12 PIN FUNCTIONS PAR/SER (Pin 35): Programming Mode Selection Pin. Connect to ground to enable the serial programming mode. CS, SCK, SDI and SDO become a serial interface that controls the A/D operating modes. Connect to VDD to enable parallel programming mode where CS, SCK, SDI and SDO become parallel logic inputs that control a reduced set of the A/D operating modes. PAR/SER should be connected directly to ground or the VDD of the part and not be driven by a logic signal.
PAGE 19
LTC2265-12/ LTC2264-12/LTC2263-12 FUNCTIONAL BLOCK DIAGRAM ENC+ ENC– 1.8V 1.8V VDD CHANNEL 1 ANALOG INPUT OVDD 12-BIT ADC CORE SAMPLEAND-HOLD PLL OUT1A OUT1B CHANNEL 2 ANALOG INPUT DATA SERIALIZER 12-BIT ADC CORE SAMPLEAND-HOLD OUT2A OUT2B VREF 1µF 1.25V REFERENCE DATA CLOCK OUT FRAME RANGE SELECT REFH REF BUF SENSE REFL OGND VDD /2 DIFF REF AMP GND MODE CONTROL REGISTERS REFH 0.1µF REFL VCM1 0.1µF 226512 F01 VCM2 0.1µF PAR/SER CS SCK SDI SDO 2.2µF 0.1µF 0.1µF Figure 1.
PAGE 20
LTC2265-12/ LTC2264-12/LTC2263-12 APPLICATIONS INFORMATION CONVERTER OPERATION Transformer Coupled Circuits The LTC2265-12/LTC2264-12/LTC2263-12 are low power, 2-channel, 12-bit, 65Msps/40Msps/25Msps A/D converters that are powered by a single 1.8V supply. The analog inputs should be driven differentially. The encode input can be driven differentially for optimal jitter performance, or single-ended for lower power consumption. To minimize the number of data lines, the digital outputs are serial LVDS.
PAGE 21
LTC2265-12/ LTC2264-12/LTC2263-12 APPLICATIONS INFORMATION Amplifier Circuits Figure 7 shows the analog input being driven by a high speed differential amplifier. The output of the amplifier is ACcoupled to the A/D so the amplifier’s output common mode voltage can be optimally set to minimize distortion. 50Ω At very high frequencies an RF gain block will often have lower distortion than a differential amplifier.
PAGE 22
LTC2265-12/ LTC2264-12/LTC2263-12 APPLICATIONS INFORMATION Reference Encode Input The LTC2265-12/LTC2264-12/LTC2263-12 has an internal 1.25V voltage reference. For a 2V input range using the internal reference, connect SENSE to VDD. For a 1V input range using the internal reference, connect SENSE to ground. For a 2V input range with an external reference, apply a 1.25V reference voltage to SENSE (Figure 9). The signal quality of the encode inputs strongly affects the A/D noise performance.
PAGE 23
LTC2265-12/ LTC2264-12/LTC2263-12 APPLICATIONS INFORMATION The differential encode mode is recommended for sinusoidal, PECL, or LVDS encode inputs (Figures 12 and 13). The encode inputs are internally biased to 1.2V through 10k equivalent resistance. The encode inputs can be taken above VDD (up to 3.6V), and the common mode range is from 1.1V to 1.6V. In the differential encode mode, ENC – should stay at least 200mV above ground to avoid falsely triggering the single-ended encode mode.
PAGE 24
LTC2265-12/ LTC2264-12/LTC2263-12 APPLICATIONS INFORMATION Table 1. Maximum Sampling Frequency for All Serialization Modes. Note That These Limits Are for the LTC2265-12. The Sampling Frequency for the Slower Speed Grades Cannot Exceed 40MHz (LTC2264-12) or 25MHz (LTC2263-12). MAXIMUM SAMPLING FREQUENCY, fS (MHz) SERIALIZATION MODE DCO FREQUENCY FR FREQUENCY SERIAL DATA RATE 2-Lane 16-Bit Serialization 65 4 • fS fS 8 • fS 2-Lane 14-Bit Serialization 65 3.5 • fS 0.
PAGE 25
LTC2265-12/ LTC2264-12/LTC2263-12 APPLICATIONS INFORMATION Digital Output Randomizer Interference from the A/D digital outputs is sometimes unavoidable. Digital interference may be from capacitive or inductive coupling or coupling through the ground plane. Even a tiny coupling factor can cause unwanted tones in the ADC output spectrum. By randomizing the digital output before it is transmitted off chip, these unwanted tones can be randomized which reduces the unwanted amplitude.
PAGE 26
LTC2265-12/ LTC2264-12/LTC2263-12 APPLICATIONS INFORMATION Serial Programming Mode To use the serial programming mode, PAR/SER should be tied to ground. The CS, SCK, SDI and SDO pins become a serial interface that program the A/D mode control registers. Data is written to a register with a 16-bit serial word. Data can also be read back from a register to verify its contents. Serial data transfer starts when CS is taken low. The data on the SDI pin is latched at the first 16 rising edges of SCK.
PAGE 27
LTC2265-12/ LTC2264-12/LTC2263-12 APPLICATIONS INFORMATION REGISTER A2: OUTPUT MODE REGISTER (ADDRESS 02h) D7 D6 D5 D4 D3 D2 D1 D0 ILVDS2 ILVDS1 ILVDS0 TERMON OUTOFF OUTMODE2 OUTMODE1 OUTMODE0 Bits 7-5 ILVDS2: ILVDS0 LVDS Output Current Bits 000 = 3.5mA LVDS Output Driver Current 001 = 4.0mA LVDS Output Driver Current 010 = 4.5mA LVDS Output Driver Current 011 = Not Used 100 = 3.0mA LVDS Output Driver Current 101 = 2.5mA LVDS Output Driver Current 110 = 2.
PAGE 28
LTC2265-12/ LTC2264-12/LTC2263-12 APPLICATIONS INFORMATION GROUNDING AND BYPASSING The LTC2265-12/LTC2264-12/LTC2263-12 requires a printed circuit board with a clean unbroken ground plane. A multilayer board with an internal ground plane in the first layer beneath the ADC is recommended. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible.
PAGE 29
LTC2265-12/ LTC2264-12/LTC2263-12 TYPICAL APPLICATIONS Silkscreen Top Inner Layer 2 GND Top Side Inner Layer 3 22654312fb 29
PAGE 30
LTC2265-12/ LTC2264-12/LTC2263-12 TYPICAL APPLICATIONS Inner Layer 4 Inner Layer 5 Power Bottom Side Silkscreen Bottom 22654312fb 30
PAGE 31
LTC2265-12/ LTC2264-12/LTC2263-12 TYPICAL APPLICATIONS LTC2265 Schematic PAR/SER C4 1µF SDO SENSE VDD C5 1µF C59 0.1µF 9 10 OUT1A– OUT1A+ SDO GND VREF PAR/SER GND REFH DCO– 27 LTC2265 REFH OVDD 26 25 REFL OGND REFL FR+ VCM2 FR– AIN2+ OUT2A+ 22 – OUT2A– 21 AIN2 VDD AIN2 AIN2 OUT2B+ 8 28 OUT2B– 7 DCO+ GND 6 VCM1 SDI C3 0.1µF C30 0.1µF 29 AIN1 SCK C2 0.1µF C1 2.
PAGE 32
LTC2265-12/ LTC2264-12/LTC2263-12 PACKAGE DESCRIPTION UJ Package 40-Lead (6mm × 6mm) Plastic QFN (Reference LTC DWG # 05-08-1728) 0.70 ± 0.05 6.50 ± 0.05 5.10 ± 0.05 4.42 ± 0.05 4.50 ± 0.05 (4 SIDES) 4.42 ± 0.05 PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 6.00 ± 0.10 (4 SIDES) 0.75 ± 0.05 R = 0.10 TYP R = 0.115 TYP 39 40 0.40 ± 0.10 PIN 1 TOP MARK (SEE NOTE 6) 1 4.50 REF (4-SIDES) 4.42 ± 0.
PAGE 33
LTC2265-12/ LTC2264-12/LTC2263-12 REVISION HISTORY REV DATE DESCRIPTION A 4/10 Revised Maximum Value for LTC2264-12 Sampling Frequency in Timing Characteristics 6 Updated Title of Curve G53 in Typical Performance Characteristics 13 Revised Descriptions and Comments in Related Parts Section 34 Revised Software Reset paragraph and Table 4 in Applications Information section 26 B 7/11 PAGE NUMBER 22654312fb 33
PAGE 34
LTC2265-12/ LTC2264-12/LTC2263-12 RELATED PARTS PART NUMBER DESCRIPTION ADCs LTC2170-14/LTC2171-14/ 14-Bit, 25Msps/40Msps/65Msps LTC2172-14 1.8V Quad ADCs, Ultralow Power COMMENTS LTC2170-12/LTC2171-12/ 12-Bit, 25Msps/40Msps/65Msps LTC2172-12 1.8V Quad ADCs, Ultralow Power 160mW/198mW/306mW, 71dB SNR, 90dB SFDR, Serial LVDS Outputs, 7mm × 8mm QFN-52 LTC2173-14/LTC2174-14/ 14-Bit, 80Msps/105Msps/125Msps LTC2175-14 1.8V Quad ADCs, Ultralow Power 316mW/450mW/558mW, 73.