Datasheet

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LTC2314-14

231414fa

For more information www.linear.com/LTC2314-14

TYPICAL APPLICATION

FEATURES DESCRIPTION

14-Bit, 4.5Msps Serial

Sampling ADC in TSOT

The LTC

2314-14 is a 14-bit, 4.5Msps, serial sampling A/D

converter that draws only 6.2mA from a wide range analog

supply adjustable from 2.7V to 5.25V. The LTC2314-14

contains an integrated bandgap and reference buffer which

provide a low cost, high performance (20ppm/°C max)

and space saving applications solution. The LTC2314-14

achieves outstanding AC performance of 77dB SINAD and

–85dB THD while sampling a 500kHz input frequency.

The extremely high sample rate-to-power ratio makes the

LTC2314-14 ideal for compact, low power, high speed

systems. The LTC2314-14 also provides both nap and

sleep modes for further optimization of the device power

within a system.

The LTC2314-14 has a high-speed SPI-compatible serial

interface that supports 1.8V, 2.5V, 3V and 5V logic. The

fast 4.5Msps throughput makes the LTC2314-14 ideally

suited for a wide variety of high speed applications.

Complete 14-/12-Bit Pin-Compatible SAR ADC Family

500ksps 2.5Msps 4.5Msps 5Msps

14-Bit LTC2312-14 LTC2313-14 LTC2314-14

12-Bit LTC2312-12 LTC2313-12 LTC2315-12

Power 3V/5V 9mW/15mW 14mW/25mW 18mW/31mW 19mW/32mW

APPLICATIONS

4.5Msps Throughput Rate

Guaranteed 14-Bit No Missing Codes

Internal Reference: 2.048V/4.096V Span

Low Noise: 77.5dB SNR

Low Power: 6.2mA at 4.5Msps and 5V

Dual Supply Range: 3V/5V operation

Sleep Mode with < 1µA Typical Supply Current

Nap Mode with Quick Wake-up < 1 conversion

Separate 1.8V to 5V Digital I/O Supply

High Speed SPI-Compatible Serial I/O

Guaranteed Operation from –40°C to 125°C

8-Lead TSOT-23 Package

Communication Systems

High Speed Data Acquisition

Handheld Terminal Interface

Medical Imaging

Uninterrupted Power Supplies

Battery Operated Systems

Automotive

L, LT, LT C , LT M, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

5V Supply, Internal Reference, 4.5Msps, 14-bit Sampling ADC

SERIAL DATA LINK TO

ASIC, PLD, MPU, DSP

OR SHIFT REGISTERS

ANALOG INPUT

0V TO 4.096V

2.2µF

231414 TA01

GND

REF

SCK

SDO

LTC2314-14

DIGITAL OUTPUT SUPPLY

1.8V TO 5V

32k Point FFT, f

= 4.5Msps, f

= 500kHz

231414 TA01a

FREQUENCY (kHz)

AMPLITUDE (dBFS)

0 22501750 2000

750 1000500250

1250 1500

–20

–40

–60

–80

–100

–120

–160

–140

= 5V

SNR = 77.5dBFS

SINAD = 76.9dBFS

THD = 84.9dB

SFDR = 88.1dB

Summary of content (22 pages)

PAGE 1
LTC2314-14 14-Bit, 4.5Msps Serial Sampling ADC in TSOT FEATURES n n n n n n n n n n n n DESCRIPTION 4.5Msps Throughput Rate Guaranteed 14-Bit No Missing Codes Internal Reference: 2.048V/4.096V Span Low Noise: 77.5dB SNR Low Power: 6.2mA at 4.5Msps and 5V Dual Supply Range: 3V/5V operation Sleep Mode with < 1µA Typical Supply Current Nap Mode with Quick Wake-up < 1 conversion Separate 1.
PAGE 2
LTC2314-14 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Notes 1, 2) Supply Voltage (VDD, OVDD)........................................6V Reference (REF) and Analog Input (AIN) Voltage (Note 3).......................................(–0.3V) to (VDD + 0.3V) Digital Input Voltage (Note 3)... (–0.3V) to (OVDD + 0.3V) Digital Output Voltage.............. (–0.3V) to (OVDD + 0.3V) Power Dissipation................................................100mW Operating Temperature Range LTC2314C...........................
PAGE 3
LTC2314-14 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER VAIN Absolute Input Range VIN Input Voltage Range IIN Analog Input DC Leakage Current CIN Analog Input Capacitance CONDITIONS MIN l (Note 11) TYP UNITS –0.05 VDD + 0.
PAGE 4
LTC2314-14 REFERENCE INPUT/OUTPUT The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER VREF CONDITIONS VREF Output Voltage 2.7V ≤ VDD ≤ 3.6V 4.75 ≤ VDD ≤ 5.25V VREF Temperature Coefficient l l MIN TYP MAX UNITS 2.040 4.080 2.048 4.096 2.056 4.112 V V 7 20 l ppm/°C VREF Output Resistance Normal Operation Overdrive Condition (VREFIN ≥ VREFOUT + 50mV) 2 52 Ω kΩ VREF Line Regulation 2.
PAGE 5
LTC2314-14 ADC TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS fSAMPLE(MAX) Maximum Sampling Frequency fSCK Shift Clock Frequency tSCK Shift Clock Period MIN TYP MAX UNITS (Notes 7, 8) l 4.5 MHz (Notes 7, 8) l 87.5 MHz l tTHROUGHPUT Minimum Throughput Time, tACQ + tCONV 11.
PAGE 6
LTC2314-14 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VDD = 5V, OVDD = 2.5V, fSMPL = 4.5Msps, unless otherwise noted. Differential Nonlinearity vs Output Code DC Histogram Near Mid-Scale (Code 8192) 2.0 1.00 7000 1.5 0.75 6000 1.0 0.50 0.5 0.25 0.0 –0.5 0.00 –0.25 –1.0 –0.50 –1.5 –0.75 0 4096 8192 12288 OUTPUT CODE 16384 –1.
PAGE 7
LTC2314-14 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VDD = 5V, OVDD = 2.5V, fSMPL = 4.5Msps, unless otherwise noted. 79 VDD = 5V SNR, SINAD (dBFS) THD –85 3RD –90 2ND –95 77 SNR SINAD VDD = 5V 76 SINAD 75 VDD = 3.6V 74 72 5 25 45 65 85 105 125 TEMPERATURE (°C) 600 OPERATION NOT ALLOWED 2 2.5 3 3.5 4 REFERENCE VOLTAGE (V) fS = 5Msps VDD = 3.6V 300 Full-Scale Error vs Temperature fS = 3Msps OPERATION NOT ALLOWED 100 0 2 2.5 3 3.
PAGE 8
LTC2314-14 TYPICAL PERFORMANCE CHARACTERISTICS unless otherwise noted. 6.25 SUPPLY CURRENT (mA) 2.5 6.00 5Msps fSCK = 87.5MHz 5.75 OPERATION NOT ALLOWED 5.50 3Msps 5.25 5.00 Output Supply Current (IOVDD) vs Output Supply Voltage (OVDD) 5Msps 3Msps fSCK = 52.5MHz 4.75 4.50 2.6 2.9 3.2 3.5 3.8 4.1 4.4 4.7 5.0 5.3 SUPPLY VOLTAGE (V) OUTPUT SUPPLY CURRENT (mA) 6.50 Supply Current (IVDD) vs Supply Voltage (VDD) TA = 25°C, VDD = 5V, OVDD = 2.5V, fSMPL = 4.5Msps, 2.0 5Msps fSCK = 87.5MHz 1.5 1.
PAGE 9
LTC2314-14 BLOCK DIAGRAM 2.2µF 2.2µF ANALOG SUPPLY RANGE 2.7V TO 5.25V DIGITAL SUPPLY RANGE 1.71V TO 5.25V 1 5 VDD OVDD 2.5V LDO ANALOG INPUT RANGE 0V TO VREF AIN + 4 14-BIT SAR ADC S/H – THREE-STATE SERIAL OUTPUT PORT SDO 6 REF SCK 2 2.2µF GND 3 2×/4× 7 TIMING LOGIC 1.024V BANDGAP CS 8 TS8 PACKAGE 231414 BD ALL CAPACITORS UNLESS NOTED ARE HIGH QUALITY, CERAMIC CHIP TYPE TIMING DIAGRAMS SCK 16TH EDGE t8 CS OVDD/2 Hi-Z SDO t9 OVDD/2 Hi-Z SDO Figure 1.
PAGE 10
LTC2314-14 APPLICATIONS INFORMATION Overview The LTC2314-14 is a low noise, high speed, 14-bit successive approximation register (SAR) ADC. The LTC2314-14 operates over a wide supply range (2.7V to 5.25V) and provides a low drift (20ppm/°C maximum), internal reference and reference buffer. The internal reference buffer is automatically configured to a 2.048V span in low supply range (2.7V to 3.6V) and to a 4.096V span in the high supply range (4.75V to 5.25V). The LTC2314-14 samples at a 4.
PAGE 11
LTC2314-14 APPLICATIONS INFORMATION t10 CS tCONV = 15.
PAGE 12
LTC2314-14 APPLICATIONS INFORMATION 4.5Msps, the timing pattern where SCK is held high during the acquisition time must be used. Table 1: Maximum Throughput vs Timing Pattern TIMING PATTERN MAXIMUM THROUGHPUT SCK high during TACQ 4.5Msps SCK low during TACQ 4.375Msps SCK continuous (tTHROUGHPUT = 20 periods) 4.375Msps Serial Data Output (SDO) The SDO output is always forced into the high impedance state while CS is high. The falling edge of CS starts the conversion and enables SDO.
PAGE 13
LTC2314-14 APPLICATIONS INFORMATION 1 CS 2 NAP MODE SCK START tACQ HOLD STATIC HIGH or LOW Z SDO 0 Z HOLD STATIC HIGH or LOW HI-Z STATE 0 231414 F08 Figure 8: LTC2314-14 Entering/Exiting Nap Mode 1 CS 2 3 4 VREF RECOVERY NAP MODE SCK SDO SLEEP MODE tWAIT START tACQ HOLD STATIC HIGH or LOW Z 0 Z 0 HI-Z STATE 231414 F09 Figure 9: LTC2314-14 Entering/Exiting Sleep Mode Single-Ended Analog Input Drive Choosing an Input Amplifier The analog input of the LTC2314-14 is easy to drive.
PAGE 14
LTC2314-14 APPLICATIONS INFORMATION critical and time domain applications where DC accuracy and settling time are most critical. The following list is a summary of the op amps that are suitable for driving the LTC2314-14. (More detailed information is available on the Linear Technology website at www.linear.com.) LT6230: 215MHz GBWP, –80dBc Distortion at 1MHz, Unity-Gain Stable, Rail-to-Rail Input and Output, 3.5mA/ Amplifier, 1.1nV/√Hz.
PAGE 15
LTC2314-14 APPLICATIONS INFORMATION ADC Reference A low noise, low temperature drift reference is critical to achieving the full data sheet performance of the ADC. The LTC2314-14 provides an excellent internal reference with a guaranteed 20ppm/°C maximum temperature coefficient. For added flexibility, an external reference may also be used. The high speed, low noise internal reference buffer is used only in the internal reference configuration.
PAGE 16
LTC2314-14 APPLICATIONS INFORMATION transition noise associated with a 14-bit resolution ADC which can be measured with a fixed DC signal applied to the input of the ADC. The resulting output codes are collected over a large number of conversions. The shape of the distribution of codes will give an indication of the magnitude of the transition noise. In Figure 12, the distribution of output codes is shown for a DC input that has been digitized 16,384 times.
PAGE 17
LTC2314-14 APPLICATIONS INFORMATION 0 –20 –40 AMPLITUDE (dBFS) If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies m • fa ± n • fb, where m and n = 0, 1, 2, 3, etc. For example, the 2nd order IMD terms include (fa ± fb).
PAGE 18
LTC2314-14 APPLICATIONS INFORMATION capacitors are essential to the low noise operation of the ADC. The analog input traces are screened by ground. For more details and information refer to DC1563, the evaluation kit for the LTC2314-14. Bypassing Considerations results. These errors are due to feed-through from the microprocessor to the successive approximation comparator.
PAGE 19
LTC2314-14 APPLICATIONS INFORMATION Figure 19. Layer 3 PWR Plane Figure 20. Layer 4 Bottom Layer REF U5 LT1790ACS6-2.048 9V TO 10V 4 VI GND GND 1 2 JP1 HD1X3-100 J4 AIN 0V TO 4.096V C6 4.7µF R14 0k VO AC R9 1k C8 10µF VCCIO C9 4.7µF C10 OPT C11 OPT C12 4.7µF DC COUPLING 1 2 3 C18 OPT C7 OPT VDD VCM 6 + R15 49.9Ω C17 1µF 3 2 1 U1 * 4 C19 47pF NPO JP2 VCM 1 2 5 VDD REF OVDD AIN CSL SCK GND 1.024V 3 SDO 231414 F21 8 CSL 7 SCK SDO 6 R16 33Ω 2.
PAGE 20
LTC2314-14 LTC2314-14 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. TS8 Package 8-Lead Plastic TSOT-23 (Reference LTC DWG # 05-08-1637 Rev A) 0.40 MAX 2.90 BSC (NOTE 4) 0.65 REF 1.22 REF 1.4 MIN 3.85 MAX 2.62 REF 2.80 BSC 1.50 – 1.75 (NOTE 4) PIN ONE ID RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR 0.22 – 0.36 8 PLCS (NOTE 3) 0.65 BSC 0.80 – 0.90 0.20 BSC 0.01 – 0.10 1.00 MAX DATUM ‘A’ 0.30 – 0.50 REF 0.09 – 0.
PAGE 21
LTC2314-14 REVISION HISTORY REV DATE DESCRIPTION PAGE NUMBER A 10/13 Added pin-compatible family table 1 Changed TJMAX to 150°C 2 Changed SINAD condition for –3dB Input Linear Bandwidth to ≥74dB Reordered/Renumbered Notes 3 3, 4, 5 231414fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use.
PAGE 22
LTC2314-14 TYPICAL APPLICATION Low-Jitter Clock Timing with RF Sine Generator Using Clock Squaring/Level-Shifting Circuit and Re-Timing Flip-Flop VCC 0.1µF 50Ω 1k NC7SVU04P5X MASTER CLOCK VCC 1k PRE D > Q CONV CLR NL17SZ74 CONV ENABLE CONTROL LOGIC (FPGA, CPLD, DSP, ETC.) CS SCK LTC2314-14 NC7SVUO4P5X SDO 33Ω 231414 TA03 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC2313-14 14-Bit, 2.