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LTC2351-14

235114fb

FEATURES

APPLICATIONS

DESCRIPTION

6-Channel, 14-Bit, 1.5Msps

Simultaneous Sampling ADC

with Shutdown

The LTC

2351-14 is a 14-bit, 1.5Msps ADC with six simul-

taneously sampled differential inputs. The device draws

only 5.5mA from a single 3V supply, and comes in a tiny

32-pin (5mm × 5mm) QFN package. A sleep shutdown

mode further reduces power consumption to 12μW. The

combination of low power and tiny package makes the

LTC2351-14 suitable for portable applications.

The LTC2351-14 contains six separate differential inputs

that are sampled simultaneously on the rising edge of the

CONV signal. These six sampled inputs are then converted

at a rate of 250ksps per channel.

The 83dB common mode rejection allows users to eliminate

ground loops and common mode noise by measuring

signals differentially from the source.

The device converts 0V to 2.5V unipolar inputs differentially,

or ±1.25V bipolar inputs also differentially, depending on the

state of the BIP pin. Any analog input may swing rail-to-rail

as long as the differential input range is maintained.

The conversion sequence can be abbreviated to convert

fewer than six channels, depending on the logic state of

the SEL2, SEL1 and SEL0 inputs.

The serial interface sends out the six conversion results in 96

clocks for compatibility with standard serial interfaces.

1.5Msps ADC with Six Simultaneously Sampled

Differential Inputs

250ksps Throughput per Channel

75dB SINAD

Low Power Dissipation: 16.5mW

3V Single Supply Operation

2.5V Internal Bandgap Reference, Can Be Overdriven

with External Reference

3-Wire SPI-Compatible Serial Interface

Internal Conversion Triggered by CONV

Sleep (12μW) Shutdown Mode

NAP (4.5mW) Shutdown Mode

0V to 2.5V Unipolar, or ±1.25V Bipolar Differential

Input Range

83dB Common Mode Rejection

Tiny 32-Pin (5mm × 5mm) QFN Package

Multiphase Power Measurement

Multiphase Motor Control

Data Acquisition Systems

Uninterruptable Power Supplies

L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners. Protected by U.S. Patents,

including 6084440, 6522187.

BLOCK DIAGRAM

–

7 6912

1619 8

CH0

–

CH0

CH1

–

CH1

–

1415

CH2

–

CH2

CH3

–

CH3

–

2021

S AND H S AND H S AND H S AND H S AND H

CH4

–

CH4

CH5

–

CH5

MUX

REF

10μF

BIP SEL2 SEL1 SEL0GND

2.5V

REFERENCE

1.5Msps

14-BIT ADC

14-BIT LATCH 5

14-BIT LATCH 4

14-BIT LATCH 3

14-BIT LATCH 2

14-BIT LATCH 1

14-BIT LATCH 0

10μF 3V

2629232233 27 28

SD0

0.1μF

SCK

DGND

OGND

CONV

THREE-

STATE

SERIAL

OUTPUT

PORT

TIMING

LOGIC

235114 TA01

–

S AND H

Summary of content (20 pages)

PAGE 1
LTC2351-14 6-Channel, 14-Bit, 1.5Msps Simultaneous Sampling ADC with Shutdown DESCRIPTION FEATURES n n n n n n n n n n n n n 1.5Msps ADC with Six Simultaneously Sampled Differential Inputs 250ksps Throughput per Channel 75dB SINAD Low Power Dissipation: 16.5mW 3V Single Supply Operation 2.5V Internal Bandgap Reference, Can Be Overdriven with External Reference 3-Wire SPI-Compatible Serial Interface Internal Conversion Triggered by CONV Sleep (12μW) Shutdown Mode NAP (4.5mW) Shutdown Mode 0V to 2.
PAGE 2
LTC2351-14 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Notes 1, 2) Supply Voltage (VDD, VCC, OVDD) ................................4V Analog and VREF Input Voltages (Note 3) ................................... –0.3V to (VDD + 0.3V) Digital Input Voltages ................... –0.3V to (VDD + 0.3V) Digital Output Voltage .................. –0.3V to (VDD + 0.3V) Power Dissipation ...............................................100mW Operation Temperature Range LTC2351C-14 .....................................
PAGE 3
LTC2351-14 ANALOG INPUT The l denotes the speciﬁcations which apply over the full operating temperature range, otherwise speciﬁcations are at TA = 25°C. With internal reference, VDD = VCC = 3V. SYMBOL PARAMETER CONDITIONS VIN Analog Differential Input Range (Notes 3, 8, 9) 2.7V ≤ VDD ≤ 3.6V, Unipolar 2.7V ≤ VDD ≤ 3.6V, Bipolar VCM Analog Common Mode + Differential Input Range IIN Analog Input Leakage Current CIN Analog Input Capacitance MIN TYP MAX UNITS 0 to 2.5 ±1.
PAGE 4
LTC2351-14 DIGITAL INPUTS AND DIGITAL OUTPUTS The l denotes the speciﬁcations which apply over the full operating temperature range, otherwise speciﬁcations are at TA = 25°C. VDD = VCC = 3V. VIN = 0V to VDD l High Level Output Voltage VDD = 3V, IOUT = –200μA l Low Level Output Voltage VDD = 2.7V, IOUT= 160μA VDD = 2.7V, IOUT = 1.
PAGE 5
LTC2351-14 TIMING CHARACTERISTICS Note 5: Integral linearity is tested with an external 2.55V reference and is deﬁned as the deviation of a code from the straight line passing through the actual endpoints of a transfer curve. The deviation is measured from the center of quantization band. Linearity is tested for CH0 only. Note 6: Guaranteed by design, not subject to test. Note 7: Recommended operating conditions.
PAGE 6
LTC2351-14 TYPICAL PERFORMANCE CHARACTERISTICS 100kHz Bipolar Sine Wave 8192 Point FFT Plot 100kHz Unipolar Sine Wave 8192 Point FFT Plot Differential Linearity vs Output Code, Unipolar Mode 0 1 –10 0.8 –20 –20 –30 –30 –40 –40 –50 –60 –70 –80 DIFFERENTIAL LINEARITY (LSB) 0 –10 MAGNITUDE (dB) MAGNITUDE (dB) VDD = 3V, TA = 25°C –50 –60 –70 –80 –90 –90 –100 –100 –110 –120 –110 0.4 0.2 0 –0.2 –0.4 –0.6 –0.
PAGE 7
LTC2351-14 PIN FUNCTIONS SDO (Pin 1): Three-State Serial Data Output. Each set of six output data words represent the six analog input channels at the start of the previous conversion. Data for CH0 comes out ﬁrst and data for CH5 comes out last. Each data word comes out MSB ﬁrst. OGND (Pin 2): Ground Return for SDO Currents. Connect to the solid ground plane. OVDD (Pin 3): Power Supply for the SDO Pin.
PAGE 8
LTC2351-14 PIN FUNCTIONS VDD (Pin 25): 3V Positive Digital Supply. This pin supplies 3V to the logic section. Bypass to DGND pin and solid analog ground plane with a 10μF ceramic capacitor (or 10μF tantalum in parallel with 0.1μF ceramic). Keep in mind that internal digital output signal currents ﬂow through this pin. Care should be taken to place the 0.1μF bypass capacitor as close to Pin 25 as possible. Pin 25 must be tied to Pin 24.
PAGE 9
LTC2351-14 BLOCK DIAGRAM 0.1μF 3V 10μF 4 5 CH0+ CH0– 24 VCC + 25 VDD S&H – 6 7 8 CH1+ CH1– + S&H – 9 CH2+ 10 CH2– 11 + S&H – MUX 12 13 14 15 CH3+ CH3– 1.5Msps 14-BIT ADC + S&H 14-BIT LATCH 0 14-BIT LATCH 1 14-BIT LATCH 2 14-BIT LATCH 3 14-BIT LATCH 4 14-BIT LATCH 5 OVDD 3V THREESTATE SERIAL OUTPUT PORT SD0 OGND 3 0.1μF 1 2 – 16 CH4+ 17 CH4– 18 CONV TIMING LOGIC + SCK S&H 30 32 – 19 20 21 CH5+ CH5– + S&H – 2.
PAGE 10
94 10 CONV 96 66 t6 t4 98 68 Hi-Z 35 1 2 36 t8 t2 D13 69 70 D13 D12 71 6 HOLD 7 8 t1 9 t10 10 D12 39 D11 40 D10 41 D9 42 D8 D6 43 44 D11 D10 45 14-BIT DATA WORD D7 72 D11 73 D10 74 D9 75 D8 D6 76 77 D5 78 14-BIT DATA WORD D7 79 D9 D7 D6 14-BIT DATA WORD D8 D5 D4 D3 D2 D1 D4 SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH4 D12 11 12 13 14 15 D5 46 D4 47 80 81 D2 82 49 D1 D0 D0 84 D13 tTHROUGHPUT t
PAGE 11
LTC2351-14 TIMING DIAGRAMS Nap Mode and Sleep Mode Waveforms SCK t1 t1 CONV NAP SLEEP t11 VREF 235114 TD02 NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS SCK to SDO Delay SCK VIH SCK VIH t8 t10 SDO t9 VOH SDO Hi-Z VOL 235114 TD03 235114fb 11
PAGE 12
LTC2351-14 APPLICATIONS INFORMATION SELECTING THE NUMBER OF CONVERTED CHANNELS (SEL2, SEL1, SEL0) These three control pins select the number of channels being converted. 000 selects only the ﬁrst channel (CH0) for conversion. Incrementing SELx selects additional channels for conversion, up to six channels. 101, 110 or 111 select all six channels for conversion. These pins must be kept in a ﬁxed state during conversion and during the subsequent conversion to read data.
PAGE 13
LTC2351-14 APPLICATIONS INFORMATION conversion, the analog inputs draw only a small leakage current. If the source impedance of the driving circuit is low, then the LTC2351-14 inputs can be driven directly. As source impedance increases, so will acquisition time. For minimum acquisition time with high source impedance, a buffer ampliﬁer must be used.
PAGE 14
LTC2351-14 APPLICATIONS INFORMATION INPUT FILTERING AND SOURCE IMPEDANCE INPUT RANGE The noise and the distortion of the input ampliﬁer and other circuitry must be considered since they will add to the LTC2351-14 noise and distortion. The small-signal bandwidth of the sample-and-hold circuit is 50MHz. Any noise or distortion products that are present at the analog inputs will be summed over this entire bandwidth. Noisy input circuitry should be ﬁltered prior to the analog inputs.
PAGE 15
LTC2351-14 APPLICATIONS INFORMATION INPUT SPAN VERSUS REFERENCE VOLTAGE The differential input range has a unipolar voltage span that equals the difference between the voltage at the reference buffer output VREF (Pin 23) and the voltage at ground. The differential input range of the ADC is 0V to 2.5V when using the internal reference. The internal ADC is referenced to these two nodes. This relationship also holds true with an external reference.
PAGE 16
LTC2351-14 APPLICATIONS INFORMATION POWER-DOWN MODES Upon power-up, the LTC2351-14 is initialized to the active state and is ready for conversion. The nap and sleep mode waveforms show the power down modes for the LTC2351-14. The SCK and CONV inputs control the power down modes (see Timing Diagrams). Two rising edges at CONV, without any intervening rising edges at SCK, put the LTC2351-14 in nap mode and the power consumption drops from 16.5mW to 4.5mW. The internal reference remains powered in nap mode.
PAGE 17
LTC2351-14 APPLICATIONS INFORMATION and then buffer this signal with the appropriate number of inverters to drive the serial clock input of the processor serial port. Use the falling edge of the clock to latch data from the serial data output (SDO) into your processor serial port. The 14-bit serial data will be received in six 16-bit words with 96 or more clocks per frame sync.
PAGE 18
LTC2351-14 APPLICATIONS INFORMATION HARDWARE INTERFACE TO TMS320C54x The LTC2351-14 is a serial output ADC whose interface has been designed for high speed buffered serial ports in fast digital signal processors (DSPs). Figure 7 shows an example of this interface using a TMS320C54X. The buffered serial port in the TMS320C54x has direct access to a 2kB segment of memory. The ADC’s serial data can be collected in two alternating 1kB segments, in real time, at the full 1.
PAGE 19
LTC2351-14 PACKAGE DESCRIPTION UH Package 32-Lead Plastic QFN (5mm × 5mm) (Reference LTC DWG # 05-08-169) 0.70 ±0.05 5.50 ±0.05 4.10 ±0.05 3.50 REF (4 SIDES) 3.45 ± 0.05 3.45 ± 0.05 PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 5.00 ± 0.10 (4 SIDES) BOTTOM VIEW—EXPOSED PAD 0.75 ± 0.05 R = 0.05 TYP 0.00 – 0.05 PIN 1 NOTCH R = 0.30 TYP OR 0.35 × 45° CHAMFER R = 0.115 TYP 31 32 0.40 ± 0.10 PIN 1 TOP MARK (NOTE 6) 1 2 3.
PAGE 20
LTC2351-14 TYPICAL APPLICATION Low Jitter Clock Timing With RF Sine Generator Using Clock Squaring/Level Shifting Circuit and Re-Timing Flip-Flop VCC 1k 0.1μF NC7SVU04P5X MASTER CLOCK 50Ω VCC 1k PRE Q D CONTROL LOGIC (FPGA, CPLD, DSP, ETC.) CONV 2351-14 Q CLR NL17SZ74 CONVERT ENABLE 235114 TA02 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1402 12-Bit, 2.2Msps Serial ADC 5V or ±5V Supply, 4.096V or ±2.5V Span LTC1403/LTC1403A 12-/14-Bit, 2.