Datasheet

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LTC2356-12/LTC2356-14

2356fb

BLOCK DIAGRAM

FEATURES

APPLICATIONS

DESCRIPTION

Serial 12-Bit/14-Bit, 3.5Msps

Sampling ADCs with Shutdown

The LTC

2356-12/LTC2356-14 are 12-bit/14-bit, 3.5Msps

serial ADCs with differential inputs. The devices draw

only 5.5mA from a single 3.3V supply and come in a

tiny 10-lead MSOP package. A Sleep shutdown feature

further reduces power consumption to 13µW. The com-

bination of speed, low power and tiny package makes the

LTC2356-12/LTC2356-14 suitable for high speed, portable

applications.

The 80dB common mode rejection allows users to eliminate

ground loops and common mode noise by measuring

signals differentially from the source.

The devices convert –1.25V to 1.25V bipolar inputs

differentially. The absolute voltage swing for A

and

–

extends from ground to the supply voltage.

The serial interface sends out the conversion results during

the 16 clock cycles following a CONV rising edge for com-

patibility with standard serial interfaces. If two additional

clock cycles for acquisition time are allowed after the data

stream in between conversions, the full sampling rate of

3.5Msps can be achieved with a 63MHz clock.

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the property

of their respective owners.

3.5Msps Conversion Rate

74.1dB SINAD at 14-Bits, 71.1dB SINAD at 12-Bits

Low Power Dissipation: 18mW

3.3V Single Supply Operation

2.5V Internal Bandgap Reference can be Overdriven

3-Wire SPI-Compatible Serial Interface

Sleep (13µW) Shutdown Mode

Nap (4mW) Shutdown Mode

80dB Common Mode Rejection

±1.25V Bipolar Input Range

Tiny 10-Lead MSOP Package

Communications

Data Acquisition Systems

Uninterrupted Power Supplies

Multiphase Motor Control

Multiplexed Data Acquisition

RFID

THD, 2nd and 3rd vs Input Frequency

for Differential Input Signals

2356 BD

–

S & H

GND

EXPOSED PAD

LTC2356-14

REF

10µF

–

14-BIT ADC

3.3V10µF

14-BIT LATCH

THREE-

STATE

SERIAL

OUTPUT

PORT

2.5V

REFERENCE

TIMING

LOGIC

SDO

CONV

SCK

5 6 11

FREQUENCY (MHz)

0.1

–80

THD, 2nd, 3rd (dB)

–74

–68

–62

–56

1 10 100

2356 G02

–86

–92

–98

–104

–50

THD

2nd

3rd

Summary of content (18 pages)

PAGE 1
LTC2356-12/LTC2356-14 Serial 12-Bit/14-Bit, 3.5Msps Sampling ADCs with Shutdown FEATURES n n n n n n n n n n n DESCRIPTION 3.5Msps Conversion Rate 74.1dB SINAD at 14-Bits, 71.1dB SINAD at 12-Bits Low Power Dissipation: 18mW 3.3V Single Supply Operation 2.5V Internal Bandgap Reference can be Overdriven 3-Wire SPI-Compatible Serial Interface Sleep (13µW) Shutdown Mode Nap (4mW) Shutdown Mode 80dB Common Mode Rejection ±1.
PAGE 2
LTC2356-12/LTC2356-14 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Notes 1, 2) TOP VIEW Supply Voltage (VDD)...................................................4V Analog and VREF Input Voltages (Note 3).....................................–0.3V to (VDD + 0.3V) Digital Input Voltages.................... – 0.3V to (VDD + 0.3V) Digital Output Voltage....................– 0.3V to (VDD + 0.3V) Power Dissipation................................................
PAGE 3
LTC2356-12/LTC2356-14 ANALOG INPUT The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. With internal reference. VDD = 3.3V. SYMBOL PARAMETER CONDITIONS VIN Analog Differential Input Range (Notes 3, 8, 9) 3.1V ≤ VDD ≤ 3.
PAGE 4
LTC2356-12/LTC2356-14 DIGITAL INPUTS AND DIGITAL OUTPUTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 3.3V. SYMBOL PARAMETER CONDITIONS VIH High Level Input Voltage VDD = 3.6V l VIL Low Level Input Voltage VDD = 3.1V l 0.6 V IIN Digital Input Current VIN = 0V to VDD l ±10 µA CIN Digital Input Capacitance VOH High Level Output Voltage VDD = 3.
PAGE 5
LTC2356-12/LTC2356-14 TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 3.3V. SYMBOL PARAMETER CONDITIONS fSAMPLE(MAX) Maximum Sampling Rate per Channel (Conversion Rate) MIN l tTHROUGHPUT Minimum Sampling Period (Conversion + Acquisiton Period) TYP 3.5 Clock Period (Note 16) l UNITS MHz l tSCK MAX 15.
PAGE 6
LTC2356-12/LTC2356-14 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VDD = 3.3V (LTC2356-14) SINAD vs Input Frequency THD, 2nd and 3rd vs Input Frequency –50 74 –56 71 –62 THD, 2nd, 3rd (dB) 77 SINAD (dB) 68 65 62 59 –74 –80 –86 56 –92 53 –98 50 0.1 1 10 FREQUENCY (MHz) THD 2nd 3rd –68 –104 0.1 100 1 10 FREQUENCY (MHz) 2356 G01 2356 G02 SNR vs Input Frequency SFDR vs Input Frequency 92 77 86 74 71 80 68 74 SNR (dB) SFDR (dB) 100 68 65 62 59 62 56 56 53 50 0.
PAGE 7
LTC2356-12/LTC2356-14 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VDD = 3.3V (LTC2356-14) Differential Linearity vs Output Code Integral Linearity vs Output Code 1.0 4 3 0.6 INTEGRAL LINEARITY (LSB) DIFFERENTIAL LINEARITY (LSB) 0.8 0.4 0.2 0 –0.2 –0.4 –0.6 2 1 0 –1 –2 –3 –0.8 –1.0 0 4096 12288 8192 OUTPUT CODE –4 16384 0 8192 4096 16384 12288 OUTPUT CODE 2356 G07 2356 G08 Differential and Integral Linearity vs Conversion Rate SINAD vs Conversion Rate, Input Frequency = 1.
PAGE 8
LTC2356-12/LTC2356-14 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VDD = 3.3V (LTC2356-12 and LTC2356-14) Internal Reference Voltage vs Load Current PSRR vs Frequency –25 2.4902 –30 2.4900 –35 2.4898 –45 VREF (V) PSRR (dB) –40 –50 –55 2.4894 –60 2.4892 –65 –70 2.4896 1 10 100 1k 10k FREQUENCY (Hz) 100k 1M 2.4890 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 LOAD CURRENT (mA) 2356 G13 2356 G14 VDD Supply Current vs Conversion Rate Internal Reference Voltage vs VDD 6 5.5 2.
PAGE 9
LTC2356-12/LTC2356-14 PIN FUNCTIONS AIN+ (Pin 1): Noninverting Analog Input. AIN+ operates fully differentially with respect to AIN– with a –1.25V to 1.25V differential swing with respect to AIN– and a 0V to VDD common mode swing. a solid analog ground plane with a 10µF ceramic capacitor (or 10µF tantalum in parallel with 0.1µF ceramic). Keep in mind that internal analog currents and digital output signal currents flow through this pin. Care should be taken to place the 0.
PAGE 10
LTC2356-12/LTC2356-14 TIMING DIAGRAM LTC2356-12 Timing Diagram t2 t3 17 18 t7 t1 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 16 17 18 1 SCK t4 t5 CONV t6 INTERNAL S/H STATUS tACQ SAMPLE HOLD SAMPLE t8 t8 SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION Hi-Z SDO D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X* HOLD t9 Hi-Z X* 2356 TD01 14-BIT DATA WORD tCONV tTHROUGHPUT *BITS MARKED "X" AFTER D0 SHOULD BE IGNORED.
PAGE 11
LTC2356-12/LTC2356-14 APPLICATIONS INFORMATION DRIVING THE ANALOG INPUT The differential analog inputs of the LTC2356-12/LTC2356-14 may be driven differentially or as a single-ended input (i.e., the AIN– input is set to VCM). Both differential analog inputs, AIN+ and AIN–, are sampled at the same instant. Any unwanted signal that is common to both inputs of each input pair will be reduced by the common mode rejection of the sample-and-hold circuit.
PAGE 12
LTC2356-12/LTC2356-14 APPLICATIONS INFORMATION INPUT FILTERING AND SOURCE IMPEDANCE The noise and the distortion of the input amplifier and other circuitry must be considered since they will add to the LTC2356-12/LTC2356-14 noise and distortion. The small-signal bandwidth of the sample-and-hold circuit is 50MHz. Any noise or distortion products that are present at the analog inputs will be summed over this entire bandwidth.
PAGE 13
LTC2356-12/LTC2356-14 APPLICATIONS INFORMATION INPUT SPAN VERSUS REFERENCE VOLTAGE The differential input range has a bipolar ± VREF/2 voltage span that equals the difference between the voltage at the reference buffer output VREF at Pin 3, and the voltage at the ground (Exposed Pad Ground). The differential input range of the ADC is ±1.25V when using the internal reference. The internal ADC is referenced to these two nodes. This relationship also holds true with an external reference.
PAGE 14
LTC2356-12/LTC2356-14 APPLICATIONS INFORMATION 0 –10 VREF BYPASS 0805 SIZE MAGNITUDE (dB) –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 185k 371k 556k FREQUENCY (Hz) 741k 2356 F06b Figure 6b. LTC2356-12 6MHz Sine Wave 4096 Point FFT Plot with the LT1819 Driving the Inputs Differentially Board Layout and Bypassing Wire wrap boards are not recommended for high resolution and/or high speed A/D converters.
PAGE 15
LTC2356-12/LTC2356-14 APPLICATIONS INFORMATION Note that, using sleep mode more frequently than every 2ms, compromises the settled accuracy of the internal reference. Note that, for slower conversion rates, the Nap and Sleep modes can be used for substantial reductions in power consumption. DIGITAL INTERFACE The LTC2356-12/LTC2356-14 has a 3-wire SPI-compatible (Serial Protocol Interface) interface. The SCK and CONV inputs and SDO output implement this interface.
PAGE 16
LTC2356-12/LTC2356-14 APPLICATIONS INFORMATION into your processor serial port. The 14-bit serial data will be received right justified, in a 16-bit word with 16 or more clocks per frame sync. It is good practice to drive the LTC2356-12/LTC2356-14 SCK input first to avoid digital noise interference during the internal bit comparison decision by the internal high speed comparator. Unlike the CONV input, the SCK input is not sensitive to jitter because the input signal is already sampled and held constant.
PAGE 17
LTC2356-12/LTC2356-14 REVISION HISTORY REV DATE DESCRIPTION PAGE NUMBER A 01/10 Revise Values in Pin Configuration Section 2 B 06/12 Changed straight binary to 2’s complement 13 2356fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PAGE 18
LTC2356-12/LTC2356-14 TYPICAL APPLICATION Low-Jitter Clock Timing with RF Sine Generator Using Clock Squaring/Level Shifting Circuit and Re-Timing Flip-Flop VCC 0.1µF 1k NC7SVU04P5X MASTER CLOCK VCC 50Ω 1k PRE D Q CONV Q CLR CONTROL LOGIC (FPGA, CPLD, DSP, ETC.) CONVERT ENABLE NL17SZ74 CONV LTC2356 SCK SDO NC7SVU04P5X 100Ω 2356 TA03 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS ADCs LTC1402 12-Bit, 2.2Msps Serial ADC 5V or ±5V Supply, 4.096V or ±2.