Datasheet

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LTC2365/LTC2366

23656fb

For more information www.linear.com/LTC2365

Features

applications

Description

1Msps/3Msps, 12-Bit Serial

Sampling ADCs in TSOT

The LTC

2365/LTC2366 are 1Msps/3Msps, 12-bit,

sampling A/D converters that draw only 2mA and 2.6mA,

respectively,

from a single 3V supply. These high perfor-

mance devices

include a high dynamic range sample-and-

hold and a high speed serial interface. The full-scale input

is 0V to V

or V

REF

. Outstanding AC performance includes

72dB SINAD and –80dB THD at sample rates of 3Msps.

The serial interface provides flexible power management

and allows maximum power efficiency at low throughput

rates. These devices are available in tiny 6- and 8-lead

TSOT-23 packages.

The serial interface, tiny TSOT-23 package and extremely

high sample rate-to-power ratio make the LTC2365/

LTC2366 ideal for compact, low power, high speed systems.

The high impedance single-ended analog input and the

ability to operate with reduced spans (down to 1.4V full

scale) allow direct connection to sensors and transducers

in many applications, eliminating the need for gain stages.

Single 3V Supply, 3Msps, 12-Bit Sampling ADC

12-Bit Resolution

1Msps/3Msps Sampling Rates

Low Noise: 73dB SNR

Low Power Dissipation: 6mW

Single Supply 2.35V to 3.6V Operation

No Data Latency

Sleep Mode with 0.1µA Typical Supply Current

Dedicated External Reference (TSOT23-8)

1V to 3.6V Digital Output Supply (TSOT23-8)

SPI/MICROWIRE Compatible Serial I/O

Guaranteed Operation from –40°C to 125°C

6- and 8-Lead TSOT-23 Packages

Communication Systems

Data Acquisition Systems

Handheld Terminal Interface

Medical Imaging

Uninterrupted Power Supplies

Battery-Operated Systems

Automotive

1MHz Sine Wave 8192 FFT Plot

12-Bit TSOT23-6/-8 ADC Family

DATA OUTPUT RATE 3Msps 1Msps 500ksps 250ksps 100ksps

Part Number LTC2366 LTC2365 LTC2362 LTC2361 LTC2360

typical application

REF

GND

LTC2366

23656 TA01

ANALOG INPUT

0V TO 3V

10µF

4.7µF

SERIAL DATA LINK TO

ASIC, PLD, MPU, DSP

OR SHIFT REGISTERS

DIGITAL OUTPUT SUPPLY

1V TO V

SDO

SCK

INPUT FREQUENCY (kHz)

–20

–40

–60

–80

–100

–120

–140

750 1250

23656 TA01b

250 500

1000 1500

MAGNITUE (dB)

= 3V

SMPL

= 3Msps

= 994kHz

SINAD = 72dB

THD = –80.3dB

L, LT, LT C , LT M, Linear Technology and the Linear logo are registered trademarks and

SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the property

of their respective owners.

Summary of content (24 pages)

PAGE 1
LTC2365/LTC2366 1Msps/3Msps, 12-Bit Serial Sampling ADCs in TSOT Features n n n n n n n n n n n n Description 12-Bit Resolution 1Msps/3Msps Sampling Rates Low Noise: 73dB SNR Low Power Dissipation: 6mW Single Supply 2.35V to 3.6V Operation No Data Latency Sleep Mode with 0.1µA Typical Supply Current Dedicated External Reference (TSOT23-8) 1V to 3.
PAGE 2
LTC2365/LTC2366 Absolute Maximum Ratings (Notes 1, 2) Supply Voltage (VDD)................................................4.0V Supply Voltage (OVDD).................Min (VDD + 0.3V, 4.0V) VREF and Analog Input Voltage (Note 3)......................................... –0.3V to (VDD + 0.3V) Digital Input Voltage..................... –0.3V to (VDD + 0.3V) Digital Output Voltage................... –0.3V to (VDD + 0.3V) Power Dissipation................................................
PAGE 3
LTC2365/LTC2366 Converter Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) LTC2365 PARAMETER CONDITIONS MIN Resolution (No Missing Codes) l TYP LTC2366 MAX 12 MIN TYP MAX UNITS 12 Bits ±0.25 ±1 ±0.25 ±1 LSB ±0.25 ±1 ±0.25 ±1 LSB Integral Linearity Error (Note 5, 6) l Differential Linearity Error (Note 6) l Transition Noise (Note 7) Offset Error (Note 6) l 2 ±3.
PAGE 4
LTC2365/LTC2366 Digital Inputs and Digital Outputs The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX VIH High Level Input Voltage 2.7V < VDD ≤ 3.6V 2.35V ≤ VDD ≤ 2.7V l l VIL Low Level Input Voltage 2.7V < VDD ≤ 3.6V 2.35V ≤ VDD ≤ 2.7V l l 0.8 0.7 V V IIH High Level Input Current VIN = VDD l 2.5 µA IIL Low Level Input Current VIN = 0V l –2.
PAGE 5
LTC2365/LTC2366 Timing Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) MIN LTC2365 TYP MAX PARAMETER CONDITIONS fSMPL(MAX) Maximum Sampling Frequency (Notes 8, 9) l 1 fSCK Shift Clock Frequency (Notes 8, 9, 10) l 0.5 tSCK Shift Clock Period l 62.5 tTHROUGHPUT Minimum Throughput Time, tACQ + tCONV l tACQ Acquisition Time l 181.5 56 ns tCONV Conversion Time l 818.
PAGE 6
LTC2365/LTC2366 Typical Performance Characteristics Integral Nonlinearity vs Output Code 1.0 1.0 1.0 0.8 0.6 0.6 0.4 0.4 0.4 0.2 0.2 0 –0.2 INL AND DNL (LSB) 0.6 0 –0.2 –0.6 –0.6 –0.8 –0.8 –0.8 –1.0 –1.0 3072 2048 OUTPUT CODE 4096 1024 0 3072 2048 OUTPUT CODE 73.1 SNR (dB) 6000 2047 2048 CODE 2049 72.8 72.9 VDD = 2.35V 72.2 461kHz Sine Wave 8192 FFT Plot 0 VDD = 3V fSMPL = 1Msps fIN = 1MHz –79 VDD = 2.35V VDD = 3.
PAGE 7
LTC2365/LTC2366 Typical Performance Characteristics Integral Nonlinearity vs Output Code 1.0 Differential Nonlinearity vs Output Code 1.0 VDD = 3V 0.8 Integral and Differential Nonlinearity vs Supply Voltage 1.0 VDD = 3V 0.8 0.8 0.6 0.4 0.4 0.4 0.2 0.2 0 –0.2 INL AND DNL (LSB) 0.6 DNL (LSB) 0.6 INL (LSB) TA = 25°C, VDD = OVDD = VREF (LTC2366, Note 4) 0 –0.2 0 –0.4 –0.6 –0.6 –0.8 –0.8 –0.8 –1.0 –1.0 3072 2048 OUTPUT CODE 4096 1024 0 3072 2048 OUTPUT CODE 23656 G10 –0.
PAGE 8
LTC2365/LTC2366 Typical Performance Characteristics Supply Current vs SCK Frequency 250 IDD (mA) 2.0 1.5 VDD = 3V VDD = 2.35V 1.0 0.5 0 0 10 0.8 200 150 VDD = 3V 100 VDD = 3.6V 50 0 50 20 30 40 SCK FREQUENCY (MHz) 1.0 16 SCKS PER CONVERSION NONLINEARITY ERROR (LSB) REFERENCE CURRENT (µA) VDD = 3.6V VDD = 2.35V 5 0 MAGNITUDE (dB) NONLINEARITY ERROR (LSB) MAX DNL MAX INL MIN DNL –0.4 –0.6 0.2 0 MAX INL MIN DNL –0.2 –0.4 MIN INL –0.6 –1.0 0.6 1.2 2.4 3.0 1.
PAGE 9
LTC2365/LTC2366 Pin Functions LTC2365/LTC2366 (S6 Package) LTC2365/LTC2366 (TS8 Package) VDD (Pin 1): Positive Supply. The VDD range is 2.35V to 3.6V. VDD also defines the input span of the ADC, 0V to VDD. Bypass to GND and to a solid ground plane with a 10µF ceramic capacitor (or 10µF tantalum in parallel with 0.1µF ceramic). VDD (Pin 1): Positive Supply. The VDD range is 2.35V to 3.6V. Bypass to GND and to a solid ground plane with a 10µF ceramic capacitor (or 10µF tantalum in parallel with 0.
PAGE 10
LTC2365/LTC2366 Block Diagram 10µF 4.7µF + AIN 4 + ANALOG INPUT RANGE OV TO VREF VDD 5 12-BIT ADC THREESTATE SERIAL OUTPUT PORT + S&H OVDD 1 – 6 SDO 7 SCK VREF 4.7µF 2 + TIMING LOGIC GND 3 8 TS8 PACKAGE CS 23656 BD Timing Diagrams t8 SCK 1.6V Hi-Z SDO 23656 TD01 Figure 1. SDO Into Hi-Z State After SCK Falling Edge t7 SCK SDO 1.6V VIH VIL 23656 TD02 Figure 2. SDO Data Valid Hold Time After SCK Falling Edge t4 SCK SDO 1.6V VOH VOL 23656 TD03 Figure 3.
PAGE 11
LTC2365/LTC2366 Applications Information Dc Performance Dynamic Performance The noise of an ADC can be evaluated in two ways: signalto-noise ratio (SNR) in the frequency domain and histogram in the time domain. The LTC2365/LTC2366 excel in both. Figures 5 and 6 demonstrate that the LTC2365/LTC2366 have an SNR of over 72dB. The noise in the time domain histogram is the transition noise associated with a 12-bit resolution ADC which can be measured with a fixed DC signal applied to the input of the ADC.
PAGE 12
LTC2365/LTC2366 Applications Information Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio (SINAD) is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency components at the A/D output. The output is band limited to frequencies from above DC and below half the sampling frequency. Figure 6 shows a typical FFT with a 3MHz sampling rate and a 1MHz input.
PAGE 13
LTC2365/LTC2366 Applications Information Intermodulation Distortion Peak Harmonic or Spurious Noise If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC.
PAGE 14
LTC2365/LTC2366 Applications Information OVERVIEW gram, while Figures 11 and 12 detail the timing diagrams of conversion cycles in 14 and 16 SCK cycles, respectively. The LTC2365/LTC2366 use a successive approximation algorithm and internal sample-and-hold circuit to convert an analog signal to a 12-bit serial output. Both devices operate from a single 2.35V to 3.6V supply. The LTC2366 samples at a rate of 3Msps with a 48MHz clock while the LTC2365 samples at a rate of 1Msps with a 16MHz clock.
PAGE 15
LTC2365/LTC2366 Applications Information t1 CS SCK tACQ tCONV t2 1 2 3 t6 4 5 t4 t3 SDO Z ZERO B11 B10 13 14 t5 t7 B9 B1 t9 tQUIET B0 Hi-Z STATE (MSB) tTHROUGHPUT 23656 F11 Figure 11. LTC2365/LTC2366 Serial Interface Timing Diagram for 14 SCK Cycles t1 CS SCK tACQ tCONV t2 1 2 3 t6 4 5 t4 t3 SDO Z ZERO 13 B11 B10 14 t7 B9 15 16 t5 B1 B0 t8 OR t9 tQUIET ZERO ZERO (MSB) Hi-Z STATE tTHROUGHPUT 23656 F12 Figure 12.
PAGE 16
LTC2365/LTC2366 Applications Information Sleep Mode Entering Sleep Mode The LTC2365/LTC2366 provide a sleep mode to conserve power during inactive periods. Upon power-up, holding CS HIGH initializes the ADC to sleep mode. In sleep mode, all bias circuitry is shut down and only leakage currents remain (0.1µA typ). The ADC achieves the fastest sampling rate in operational mode (full power-up). The device can also be put into sleep mode for power savings during inactive periods.
PAGE 17
LTC2365/LTC2366 Applications Information Exiting Sleep Mode and Power-Up Time POWER versus SAMPLING RATE To exit sleep mode, pull CS LOW and perform a dummy conversion. The LTC2365/LTC2366 device power up completely after the 16th falling edge of SCK. After powering up, the ADC can continuously acquire an input signal and perform conversions as described in the SERIAL INTERFACE section (see Figure 15). The wake-up time is 333ns for the LTC2366 with a 48MHz SCK and 1µs for the LTC2365 with a 16MHz SCK.
PAGE 18
LTC2365/LTC2366 Applications Information Single-ended Analog Input LTC1566-1: Low Noise 2.3MHz Continuous Time Lowpass Filter. Driving the Analog Input The analog input of the LTC2365/LTC2366 is easy to drive. The input draws only one small current spike while charging the sample-and-hold capacitor at the end of conversion. During the conversion, the analog input draws only a small leakage current.
PAGE 19
LTC2365/LTC2366 Applications Information Input Filtering and Source Impedance Reference Input The noise and the distortion of the input amplifier and other circuitry must be considered since they will add to the LTC2365/LTC2366 noise and distortion. The small-signal bandwidth of the sample-and-hold circuit is 50MHz. Any noise or distortion products that are present at the analog inputs will be summed over this entire bandwidth.
PAGE 20
LTC2365/LTC2366 Applications Information Board Layout And Bypassing be used. The capacitors must be located as close to the pins as possible. The traces connecting the pins and the bypass capacitors must be kept short and should be made as wide as possible. Wire wrap boards are not recommended for high resolution and/or high speed A/D converters. To obtain the best performance from the LTC2365/LTC2366, a printed circuit board with ground plane is required.
PAGE 21
LTC2365/LTC2366 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. S6 Package 6-Lead Plastic TSOT-23 (Reference LTC DWG # 05-08-1636) 0.62 MAX 2.90 BSC (NOTE 4) 0.95 REF 1.22 REF 3.85 MAX 2.62 REF 1.4 MIN 2.80 BSC 1.50 – 1.75 (NOTE 4) PIN ONE ID RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR 0.30 – 0.45 6 PLCS (NOTE 3) 0.95 BSC 0.80 – 0.90 0.20 BSC 0.01 – 0.10 1.00 MAX DATUM ‘A’ 0.30 – 0.50 REF 0.09 – 0.
PAGE 22
LTC2365/LTC2366 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. TS8 Package 8-Lead Plastic TSOT-23 (Reference LTC DWG # 05-08-1637 Rev A) 0.40 MAX 2.90 BSC (NOTE 4) 0.65 REF 1.22 REF 1.4 MIN 3.85 MAX 2.62 REF 2.80 BSC 1.50 – 1.75 (NOTE 4) PIN ONE ID RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR 0.22 – 0.36 8 PLCS (NOTE 3) 0.65 BSC 0.80 – 0.90 0.20 BSC 0.01 – 0.10 1.00 MAX DATUM ‘A’ 0.30 – 0.50 REF 0.09 – 0.
PAGE 23
LTC2365/LTC2366 Revision History (Revision history begins at Rev B) REV DATE DESCRIPTION B 12/13 Updated TS8 package drawing PAGE NUMBER 22 23656fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. For more information www.linear.
PAGE 24
LTC2365/LTC2366 TYPICAL APPLICATION Low Jitter Clock Timing with RF Sine Generator Using Clock Squaring/Level Shifting Circuit and Re-Timing Flip-Flop VCC 0.1µF 1k 50Ω NC7SVU04P5X MASTER CLOCK VCC 1k D PRE Q Q CONV CLR CONTROL LOGIC (FPGA, CPLD, DSP, ETC.) CONVERT ENABLE NL17SZ74 CONV LTC2366 SCK SDO NC7SVU04P5X 100Ω 23656 TA02 Related Parts PART NUMBER DESCRIPTION COMMENTS LTC1402 12-Bit, 2.2Msps Serial ADC 5V or ±5V Supply, 4.096V or ±2.5V Span LTC1403/LTC1403A 12-/14-Bit, 2.