Datasheet

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LTC2367-18

236718f

18-Bit, 500ksps, Pseudo-

Differential Unipolar SAR

ADC with 97dB SNR

TYPICAL APPLICATION

FEATURES DESCRIPTION

The LTC

2367-18 is a low noise, low power, high speed

18-bit successive approximation register (SAR) ADC.

Operating from a 2.5V supply, the LTC2367-18 has a 0V

to V

REF

pseudo-differential unipolar input range with V

REF

ranging from 2.5V to 5.1V. The LTC2367-18 consumes only

6.8mW and achieves ±2.5LSB INL maximum, no missing

codes at 18 bits with 97dB SNR.

The LTC2367-18 has a high speed SPI-compatible se-

rial interface that supports 1.8V, 2.5V, 3.3V and 5V logic

while also featuring a daisy-chain mode. The fast 500ksps

throughput with no cycle latency makes the LTC2367-18

ideally suited for a wide variety of high speed applications.

An internal oscillator sets the conversion time, easing exter-

nal timing considerations. The LTC2367-18 automatically

powers down between conversions, leading to reduced

power dissipation that scales with the sampling rate.

32k Point FFT f

= 500ksps, f

= 2kHz

APPLICATIONS

500ksps Throughput Rate

±2.5LSB INL (Max)

Guaranteed 18-Bit No Missing Codes

Low Power: 6.8mW at 500ksps, 6.8µW at 500sps

97dB SNR (Typ) at f

= 2kHz

–120dB THD (Typ) at f

= 2kHz

Guaranteed Operation to 125°C

2.5V Supply

Pseudo-Differential Unipolar Input Range: 0V to V

REF

Input Range from 2.5V to 5.1V

No Pipeline Delay, No Cycle Latency

1.8V to 5V I/O Voltages

SPI-Compatible Serial I/O with Daisy-Chain Mode

Internal Conversion Clock

16-Lead MSOP and 4mm × 3mm DFN Packages

Medical Imaging

High Speed Data Acquisition

Portable or Compact Instrumentation

Industrial Process Control

Low Power Battery-Operated Instrumentation

ATE

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the

property of their respective owners. Protected by U.S. Patents, including 7705765.

10Ω

REF

10nF

–

SAMPLE CLOCK

236718 TA01a

10µF 0.1µF

2.5V

REF

1.8V TO 5V

2.5V TO 5.1V

47µF

(X5R, 0805 SIZE)

REF GND

CHAIN

RDL/SDI

SDO

SCK

BUSY

CNV

LTC2367-18

6202

–

FREQUENCY (kHz)

0 50 100 150 200 250

–180

AMPLITUDE (dBFS)

–60

–40

–20

–80

–100

–120

–140

–160

236718 TA01b

SNR = 97.2dB

THD = –120dB

SINAD = 97.1dB

SFDR = 122dB

Summary of content (24 pages)

PAGE 1
LTC2367-18 18-Bit, 500ksps, PseudoDifferential Unipolar SAR ADC with 97dB SNR FEATURES n n n n n n n n n n n n n n n DESCRIPTION 500ksps Throughput Rate ±2.5LSB INL (Max) Guaranteed 18-Bit No Missing Codes Low Power: 6.8mW at 500ksps, 6.8µW at 500sps 97dB SNR (Typ) at fIN = 2kHz –120dB THD (Typ) at fIN = 2kHz Guaranteed Operation to 125°C 2.5V Supply Pseudo-Differential Unipolar Input Range: 0V to VREF VREF Input Range from 2.5V to 5.1V No Pipeline Delay, No Cycle Latency 1.
PAGE 2
LTC2367-18 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) Supply Voltage (VDD)................................................2.8V Supply Voltage (OVDD).................................................6V Reference Input (REF)..................................................6V Analog Input Voltage (Note 3) IN+, IN–..........................(GND – 0.3V) to (REF + 0.3V) Digital Input Voltage (Note 3)........................... (GND – 0.3V) to (OVDD + 0.3V) Digital Output Voltage (Note 3)...........................
PAGE 3
LTC2367-18 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS VIN+ Absolute Input Range (IN+) MIN TYP MAX UNITS (Note 5) l –0.
PAGE 4
LTC2367-18 REFERENCE INPUT The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS VREF Reference Voltage (Note 5) l MIN IREF Reference Input Current (Note 9) l TYP 2.5 0.24 MAX UNITS 5.1 V 0.32 mA DIGITAL INPUTS AND DIGITAL OUTPUTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
PAGE 5
LTC2367-18 ADC TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS tSCK SCK Period (Notes 11, 12) tSCKH tSCKL tSSDISCK SDI Setup Time From SCK↑ tHSDISCK MIN TYP MAX UNITS l 10 ns SCK High Time l 4 ns SCK Low Time l 4 ns (Note 11) l 4 ns SDI Hold Time From SCK↑ (Note 11) l 1 ns 13.
PAGE 6
LTC2367-18 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VDD = 2.5V, OVDD = 2.5V, REF = 5V, fSMPL = 500ksps, unless otherwise noted. Integral Nonlinearity vs Output Code Differential Nonlinearity vs Output Code 0.5 40000 1.5 0.4 35000 0.3 0.5 0.0 –0.5 –1.0 0.0 –0.1 10000 5000 –0.4 65536 131072 196608 OUTPUT CODE –0.
PAGE 7
LTC2367-18 TYPICAL PERFORMANCE CHARACTERISTICS fSMPL = 500ksps, unless otherwise noted. THD, Harmonics vs Temperature, fIN = 2kHz 99.0 –110 98.5 –115 THD –120 2ND 97.5 SNR SINAD 97.0 96.5 96.0 –125 –130 3RD –135 95.0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) –145 –55 –35 –15 Full-Scale Error vs Temperature –0.5 MIN INL Supply Current vs Temperature Offset Error vs Temperature 3.
PAGE 8
LTC2367-18 PIN FUNCTIONS CHAIN (Pin 1): Chain Mode Selector Pin. When low, the LTC2367-18 operates in normal mode and the RDL/SDI input pin functions to enable or disable SDO. When high, the LTC2367-18 operates in chain mode and the RDL/SDI pin functions as SDI, the daisy-chain serial data input. Logic levels are determined by OVDD. VDD (Pin 2): 2.5V Power Supply. The range of VDD is 2.375V to 2.625V. Bypass VDD to GND with a 10µF ceramic capacitor. GND (Pins 3, 6, 10 and 16): Ground.
PAGE 9
LTC2367-18 FUNCTIONAL BLOCK DIAGRAM VDD = 2.5V REF = 5V IN+ + 18-BIT SAMPLING ADC IN– – OVDD = 1.
PAGE 10
LTC2367-18 APPLICATIONS INFORMATION OVERVIEW Fast 500ksps throughput with no cycle latency makes the LTC2367-18 ideally suited for a wide variety of high speed applications. An internal oscillator sets the conversion time, easing external timing considerations. The LTC2367-18 dissipates only 6.8mW at 500ksps, while an auto power-down feature is provided to further reduce power dissipation during inactive periods. CONVERTER OPERATION The LTC2367-18 operates in two phases.
PAGE 11
LTC2367-18 APPLICATIONS INFORMATION INPUT DRIVE CIRCUITS A low impedance source can directly drive the high impedance input of the LTC2367-18 without gain error. A high impedance source should be buffered to minimize settling time during acquisition and to optimize the distortion performance of the ADC. Minimizing settling time is important even for DC inputs, because the ADC input draws a current spike when entering acquisition.
PAGE 12
LTC2367-18 APPLICATIONS INFORMATION VCM = VREF/2 200pF R2 499Ω R4 402Ω ADC REFERENCE 3 R3 2k 10µF + LT6202 RIN 2k 10V 0V –10V 4 – 5V 1 0V R1 499Ω 200pF 236718 F05a Figure 5a. LT6202 Converting a ±10V Bipolar Signal to a 0V to 5V Input Signal 0 SNR = 96.8dB THD = –99dB SINAD = 93.8dB SFDR = 99.6dB –20 AMPLITUDE (dBFS) –40 –60 –80 The REF pin of the LTC2367-18 draws charge (QCONV) from the 47µF bypass capacitor during each conversion cycle.
PAGE 13
LTC2367-18 APPLICATIONS INFORMATION In applications where power management is critical and the external reference may be powered down, it is recommended that REF is kept greater than 2V in order to guarantee a maximum shutdown current of 140µA. In such applications, a Schottky diode can be placed between REF and VDD, as shown in Figure 7. SNR = 97.2dB THD = –120dB SINAD = 97.1dB SFDR = 122dB –20 –40 AMPLITUDE (dBFS) code.
PAGE 14
LTC2367-18 APPLICATIONS INFORMATION Power Supply Sequencing Auto Power-Down The LTC2367-18 does not have any specific power supply sequencing requirements. Care should be taken to adhere to the maximum voltage relationships described in the Absolute Maximum Ratings section. The LTC2367‑18 has a power-on-reset (POR) circuit that will reset the LTC2367-18 at initial power-up or whenever the power supply voltage drops below 1V.
PAGE 15
LTC2367-18 TIMING DIAGRAMS The serial interface on the LTC2367-18 is simple and straightforward to use. The following sections describe the operation of the LTC2367-18. Several modes are provided depending on whether a single or multiple ADCs share the SPI bus or are daisy chained. serial data output pin SDO. If RDL/SDI is high, SDO is in high impedance. If RDL/SDI is low, SDO is driven. Figure 10 shows a single LTC2367-18 operated in normal mode with CHAIN and RDL/SDI tied to ground.
PAGE 16
LTC2367-18 TIMING DIAGRAMS Normal Mode, Multiple Devices be used to allow only one LTC2367-18 to drive SDO at a time in order to avoid bus conflicts. As shown in Figure 11, the RDL/SDI inputs idle high and are individually brought low to read data out of each device between conversions. When RDL/SDI is brought low, the MSB of the selected device is output onto SDO. Figure 11 shows multiple LTC2367-18 devices operating in normal mode (CHAIN = 0) sharing CNV, SCK and SDO.
PAGE 17
LTC2367-18 TIMING DIAGRAMS Chain Mode, Multiple Devices number of converters. Figure 12 shows an example with two daisy-chained devices. The MSB of converter A will appear at SDO of converter B after 18 SCK cycles. The MSB of converter A is clocked in at the SDI/RDL pin of converter B on the rising edge of the first SCK. When CHAIN = OVDD, the LTC2367-18 operates in chain mode.
PAGE 18
LTC2367-18 BOARD LAYOUT To obtain the best performance from the LTC2367-18 a printed circuit board is recommended. Layout for the printed circuit board (PCB) should ensure the digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital clocks or signals alongside analog signals or underneath the ADC. Recommended Layout The following is an example of a recommended PCB layout. A single solid ground plane is used.
PAGE 19
LTC2367-18 BOARD LAYOUT Partial Layer 1 Component Side Partial Layer 2 Ground Plane 236718f 19
PAGE 20
LTC2367-18 BOARD LAYOUT Partial Layer 3 PWR Plane Partial Layer 4 Bottom Layer 236718f 20
PAGE 21
J8 AIN – E7 EXT VREF/2 R14 0Ω R39 0Ω JP5 HD1X3-100 EXT_CM AIN+ J4 COUPLING AC DC C46 1µF 3 2 1 C8 1µF +2.5V R15 OPT HD1X3-100 JP2 CM C18 OPT C17 10µF JP1 HD1X3-100 C47 OPT C48 10µF 6.3V 4 2 5 4 +3.3V C2 0.1µF R3 CLK 33Ω TO CPLD R41 OPT R40 OPT R9 OPT C49 OPT C63 10µF 6.3V 2 C44 1µF V+ 4 C59 1µF –IN1 OUT1 1 C57 0.1µF V– C43 0.1µF C55 1µF 3 +IN1 V– C61 10µF 6.3V C42 15pF R32 0Ω U15 5 LT6202CS5 V+ V+ U2 R6 3 U8 3 NC7SZ04P5X NC7SVU04P5X 1k 5 +3.3V C1 0.
PAGE 22
LTC2367-18 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. DE Package 16-Lead Plastic DFN (4mm × 3mm) (Reference LTC DWG # 05-08-1732 Rev Ø) 0.70 ±0.05 3.30 ±0.05 3.60 ±0.05 2.20 ±0.05 1.70 ± 0.05 PACKAGE OUTLINE 0.25 ± 0.05 0.45 BSC 3.15 REF RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 ±0.10 (2 SIDES) R = 0.05 TYP 9 R = 0.115 TYP 0.40 ± 0.10 16 3.30 ±0.10 3.00 ±0.
PAGE 23
LTC2367-18 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. MS Package 16-Lead Plastic MSOP (Reference LTC DWG # 05-08-1669 Rev Ø) 0.889 ± 0.127 (.035 ± .005) 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) 4.039 ± 0.102 (.159 ± .004) (NOTE 3) 0.50 (.0197) BSC 0.305 ± 0.038 (.0120 ± .0015) TYP RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) DETAIL “A” 3.00 ± 0.102 (.118 ± .004) (NOTE 4) 4.90 ± 0.152 (.193 ± .006) 0° – 6° TYP 0.
PAGE 24
LTC2367-18 TYPICAL APPLICATION LT6202 Converting a ±10V Bipolar Signal to a 0V to 5V Input Signal Into the LTC2367-18 LTC6655-5 VIN VOUT_F VOUT_S 8V 5V 200pF R2 3k 10µF 47µF 5 V+ R4 402Ω 3 R3 2k LT6202 + 1 4 2.5V 5V 0V 10Ω – IN+ 10nF REF VDD LTC2367-18 IN– V– 2 10V 0V –10V RIN 2k R1 499Ω 236718 TA02 –3V 220pF RELATED PARTS PART NUMBER ADCs LTC2379-18/LTC2378-18 LTC2377-18/LTC2376-18 DESCRIPTION COMMENTS 18-Bit, 1.6Msps/1Msps/500ksps/250ksps Serial, Low 2.