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LTC2368-16

236816f

16-Bit, 1Msps, Pseudo-

Differential Unipolar SAR

ADC with 94.7dB SNR

TYPICAL APPLICATION

FEATURES DESCRIPTION

The LTC

2368-16 is a low noise, low power, high speed

16-bit successive approximation register (SAR) ADC.

Operating from a 2.5V supply, the LTC2368-16 has a 0V

to V

REF

pseudo-differential unipolar input range with V

REF

ranging from 2.5V to 5.1V. The LTC2368-16 consumes

only 13.5mW and achieves ±0.75LSB INL maximum, no

missing codes at 16 bits with 94.7dB SNR.

The LTC2368-16 has

a high speed SPI-compatible serial

interface that supports 1.8V, 2.5V, 3.3V and 5V logic

while also featuring a daisy-chain mode. The fast 2Msps

throughput with no cycle latency makes the LTC2368-16

ideally suited for a wide variety of high speed applications.

An internal oscillator sets the conversion time, easing exter-

nal timing considerations. The LTC2368-16 automatically

powers down between conversions, leading to reduced

power

dissipation that scales with the sampling rate.

32k Point FFT f

= 1Msps, f

= 2kHz

APPLICATIONS

1Msps Throughput Rate

±0.75LSB INL (Max)

Guaranteed 16-Bit No Missing Codes

Low Power: 13.5mW at 1Msps, 13.5µW at 1ksps

94.7dB SNR (Typ) at f

= 2kHz

–118dB THD (Typ) at f

= 2kHz

Guaranteed Operation to 125°C

2.5V Supply

Pseudo-Differential Unipolar Input Range: 0V to V

REF

Input Range from 2.5V to 5.1V

No Pipeline Delay, No Cycle Latency

1.8V to 5V I/O Voltages

SPI-Compatible Serial I/O with Daisy-Chain Mode

Internal Conversion Clock

16-Lead MSOP and 4mm × 3mm DFN Packages

Medical Imaging

High Speed Data Acquisition

Portable or Compact Instrumentation

Industrial Process Control

Low Power Battery-Operated Instrumentation

ATE

L, LT, LTC, LTM , Linear Technology and the Linear logo are registered trademarks and

SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the

property of their respective owners. Protected by U.S. Patents, including 7705765.

10Ω

REF

10nF

–

SAMPLE CLOCK

236816 TA01a

10µF 0.1µF

2.5V

REF

1.8V TO 5V

2.5V TO 5.1V

47µF

(X5R, 0805 SIZE)

REF GND

CHAIN

RDL/SDI

SDO

SCK

BUSY

CNV

LTC2368-16

6202

–

FREQUENCY (kHz)

0 100 200 300 400 500

–180

AMPLITUDE (dBFS)

–60

–40

–20

–80

–100

–120

–140

–160

236816 TA01b

SNR = 94.7dB

THD = –118dB

SINAD = 94.7dB

SFDR = 119dB

Summary of content (24 pages)

PAGE 1
LTC2368-16 16-Bit, 1Msps, PseudoDifferential Unipolar SAR ADC with 94.7dB SNR FEATURES n n n n n n n n n n n n n n n DESCRIPTION 1Msps Throughput Rate ±0.75LSB INL (Max) Guaranteed 16-Bit No Missing Codes Low Power: 13.5mW at 1Msps, 13.5µW at 1ksps 94.7dB SNR (Typ) at fIN = 2kHz –118dB THD (Typ) at fIN = 2kHz Guaranteed Operation to 125°C 2.5V Supply Pseudo-Differential Unipolar Input Range: 0V to VREF VREF Input Range from 2.5V to 5.1V No Pipeline Delay, No Cycle Latency 1.
PAGE 2
LTC2368-16 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) Supply Voltage (VDD)................................................2.8V Supply Voltage (OVDD).................................................6V Reference Input (REF)..................................................6V Analog Input Voltage (Note 3) IN+, IN–..........................(GND – 0.3V) to (REF + 0.3V) Digital Input Voltage (Note 3)........................... (GND – 0.3V) to (OVDD + 0.3V) Digital Output Voltage (Note 3)...........................
PAGE 3
LTC2368-16 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS VIN+ Absolute Input Range (IN+) MIN TYP MAX UNITS (Note 5) l –0.
PAGE 4
LTC2368-16 REFERENCE INPUT The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS VREF Reference Voltage (Note 5) l MIN IREF Reference Input Current (Note 9) l TYP 2.5 0.5 MAX UNITS 5.1 V 0.7 mA DIGITAL INPUTS AND DIGITAL OUTPUTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
PAGE 5
LTC2368-16 ADC TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER tSCKL SCK Low Time CONDITIONS tSSDISCK SDI Setup Time From SCK↑ tHSDISCK tSCKCH MIN TYP MAX UNITS l 4 ns (Note 11) l 4 ns SDI Hold Time From SCK↑ (Note 11) l 1 ns SCK Period in Chain Mode tSCKCH = tSSDISCK + tDSDO (Note 11) l 13.
PAGE 6
LTC2368-16 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VDD = 2.5V, OVDD = 2.5V, REF = 5V, fSMPL = 1Msps, unless otherwise noted. Differential Nonlinearity vs Output Code DC Histogram 0.5 100000 0.8 0.4 90000 0.6 0.3 80000 0.4 0.2 70000 0.1 60000 0.2 0.0 –0.2 COUNTS 1.0 DNL ERROR (LSB) 0.0 –0.1 –0.2 30000 –0.3 20000 –0.8 –0.4 10000 –1.0 –0.
PAGE 7
LTC2368-16 TYPICAL PERFORMANCE CHARACTERISTICS fSMPL = 1Msps, unless otherwise noted. SNR, SINAD vs Temperature, fIN = 2kHz THD, Harmonics vs Temperature, fIN = 2kHz 96.0 94.5 94.0 93.5 –115 THD –120 2ND INL/DNL ERROR (LSB) HARMONICS, THD (dBFS) SNR, SINAD (dBFS) SNR SINAD –125 –130 3RD –135 5 25 45 65 85 105 125 TEMPERATURE (°C) –145 –55 –35 –15 MIN DNL MIN INL –0.
PAGE 8
LTC2368-16 PIN FUNCTIONS CHAIN (Pin 1): Chain Mode Selector Pin. When low, the LTC2368-16 operates in normal mode and the RDL/SDI input pin functions to enable or disable SDO. When high, the LTC2368-16 operates in chain mode and the RDL/SDI pin functions as SDI, the daisy-chain serial data input. Logic levels are determined by OVDD. VDD (Pin 2): 2.5V Power Supply. The range of VDD is 2.375V to 2.625V. Bypass VDD to GND with a 10µF ceramic capacitor. GND (Pins 3, 6, 10 and 16): Ground.
PAGE 9
LTC2368-16 FUNCTIONAL BLOCK DIAGRAM VDD = 2.5V OVDD = 1.
PAGE 10
LTC2368-16 APPLICATIONS INFORMATION OVERVIEW Fast 1Msps throughput with no cycle latency makes the LTC2368-16 ideally suited for a wide variety of high speed applications. An internal oscillator sets the conversion time, easing external timing considerations. The LTC2368-16 dissipates only 13.5mW at 1Msps, while an auto powerdown feature is provided to further reduce power dissipation during inactive periods. CONVERTER OPERATION The LTC2368-16 operates in two phases.
PAGE 11
LTC2368-16 APPLICATIONS INFORMATION INPUT DRIVE CIRCUITS A low impedance source can directly drive the high impedance input of the LTC2368-16 without gain error. A high impedance source should be buffered to minimize settling time during acquisition and to optimize the distortion performance of the ADC. Minimizing settling time is important even for DC inputs, because the ADC input draws a current spike when entering acquisition.
PAGE 12
LTC2368-16 APPLICATIONS INFORMATION VCM = VREF/2 200pF R2 499Ω R4 402Ω ADC REFERENCE 3 R3 2k 10µF + LT6202 RIN 2k 10V 0V –10V 4 – 5V 1 0V R1 499Ω 200pF 236816 F05a Figure 5a. LT6202 Converting a ±10V Bipolar Signal to a 0V to 5V Input Signal 0 SNR = 94.6dB THD = –99dB SINAD = 92.1dB SFDR = 99.6dB –20 AMPLITUDE (dBFS) –40 –60 –80 The REF pin of the LTC2368-16 draws charge (QCONV) from the 47µF bypass capacitor during each conversion cycle.
PAGE 13
LTC2368-16 APPLICATIONS INFORMATION In applications where power management is critical and the external reference may be powered down, it is recommended that REF is kept greater than 2V in order to guarantee a maximum shutdown current of 140µA. In such applications, a Schottky diode can be placed between REF and VDD, as shown in Figure 7. REF VDD the RMS amplitude of all other frequency components except the first five harmonics and DC. Figure 8 shows that the LTC2368-16 achieves a typical SNR of 94.
PAGE 14
LTC2368-16 APPLICATIONS INFORMATION TIMING AND CONTROL CNV Timing The LTC2368-16 conversion is controlled by CNV. A rising edge on CNV will start a conversion and power up the LTC2368-16. Once a conversion has been initiated, it cannot be restarted until the conversion is complete. For optimum performance, CNV should be driven by a clean low jitter signal. Converter status is indicated by the BUSY output which remains high while the conversion is in progress.
PAGE 15
LTC2368-16 TIMING DIAGRAMS Normal Mode, Single Device Figure 10 shows a single LTC2368-16 operated in normal mode with CHAIN and RDL/SDI tied to ground. With RDL/SDI grounded, SDO is enabled and the MSB(D15) of the new conversion data is available at the falling edge of BUSY. This is the simplest way to operate the LTC2368-16. When CHAIN = 0, the LTC2368-16 operates in normal mode. In normal mode, RDL/SDI enables or disables the serial data output pin SDO. If RDL/SDI is high, SDO is in high impedance.
PAGE 16
LTC2368-16 TIMING DIAGRAMS Normal Mode, Multiple Devices be used to allow only one LTC2368-16 to drive SDO at a time in order to avoid bus conflicts. As shown in Figure 11, the RDL/SDI inputs idle high and are individually brought low to read data out of each device between conversions. When RDL/SDI is brought low, the MSB of the selected device is output onto SDO. Figure 11 shows multiple LTC2368-16 devices operating in normal mode (CHAIN = 0) sharing CNV, SCK and SDO.
PAGE 17
LTC2368-16 TIMING DIAGRAMS Chain Mode, Multiple Devices number of converters. Figure 12 shows an example with two daisy-chained devices. The MSB of converter A will appear at SDO of converter B after 16 SCK cycles. The MSB of converter A is clocked in at the SDI/RDL pin of converter B on the rising edge of the first SCK. When CHAIN = OVDD, the LTC2368-16 operates in chain mode.
PAGE 18
LTC2368-16 BOARD LAYOUT To obtain the best performance from the LTC2368-16 a printed circuit board is recommended. Layout for the printed circuit board (PCB) should ensure the digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital clocks or signals alongside analog signals or underneath the ADC. Recommended Layout The following is an example of a recommended PCB layout. A single solid ground plane is used.
PAGE 19
LTC2368-16 BOARD LAYOUT Partial Layer 1 Component Side Partial Layer 2 Ground Plane 236816f 19
PAGE 20
LTC2368-16 BOARD LAYOUT Partial Layer 3 PWR Plane Partial Layer 4 Bottom Layer 236816f 20
PAGE 21
AIN – J8 E7 EXT VREF/2 R14 0Ω R39 0Ω JP5 HD1X3-100 EXT_CM AIN+ J4 COUPLING AC DC C46 1µF 3 2 1 C8 1µF +2.5V R15 OPT HD1X3-100 JP2 CM C18 OPT C17 10µF COUPLING AC DC 1 JP1 HD1X3-100 C47 OPT C48 10µF 6.3V 5 4 +3.3V C1 0.1µF 2 5 4 +3.3V C2 0.1µF R3 CLK 33Ω TO CPLD R41 OPT R40 OPT R9 OPT C49 OPT C63 10µF 6.3V C44 1µF V+ 4 C59 1µF –IN1 OUT1 1 C57 0.1µF 2 V– V+ C43 0.1µF C55 1µF 3 +IN1 V– C61 10µF 6.
PAGE 22
LTC2368-16 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. DE Package 16-Lead Plastic DFN (4mm × 3mm) (Reference LTC DWG # 05-08-1732 Rev Ø) 0.70 ±0.05 3.30 ±0.05 3.60 ±0.05 2.20 ±0.05 1.70 ± 0.05 PACKAGE OUTLINE 0.25 ± 0.05 0.45 BSC 3.15 REF RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 ±0.10 (2 SIDES) R = 0.05 TYP 9 R = 0.115 TYP 0.40 ± 0.10 16 3.30 ±0.10 3.00 ±0.
PAGE 23
LTC2368-16 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. MS Package 16-Lead Plastic MSOP (Reference LTC DWG # 05-08-1669 Rev Ø) 0.889 ± 0.127 (.035 ± .005) 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) 4.039 ± 0.102 (.159 ± .004) (NOTE 3) 0.50 (.0197) BSC 0.305 ± 0.038 (.0120 ± .0015) TYP RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) DETAIL “A” 3.00 ± 0.102 (.118 ± .004) (NOTE 4) 4.90 ± 0.152 (.193 ± .006) 0° – 6° TYP 0.
PAGE 24
LTC2368-16 TYPICAL APPLICATION LT6202 Converting a ±10V Bipolar Signal to a 0V to 5V Input Signal Into the LTC2368-16 LTC6655-5 VIN VOUT_F VOUT_S 8V 5V 200pF R2 3k 10µF 47µF 5 V+ R4 402Ω 3 R3 2k LT6202 + 1 4 2.