Datasheet

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LTC2369-18

236918fa

18-Bit, 1.6Msps, Pseudo-

Differential Unipolar SAR

ADC with 96.5dB SNR

TYPICAL APPLICATION

FEATURES DESCRIPTION

The LTC

2369-18 is a low noise, low power, high speed

18-bit successive approximation register (SAR) ADC.

Operating from a 2.5V supply, the LTC2369-18 has a 0V

to V

REF

pseudo-differential unipolar input range with V

REF

ranging from 2.5V to 5.1V. The LTC2369-18 consumes only

18mW and achieves ±2.5LSB INL maximum, no missing

codes at 18 bits with 96.5dB SNR.

The LTC2369-18 has a high speed SPI-compatible serial

interface that supports 1.8V, 2.5V, 3.3V and 5V logic while

also featuring a daisy-chain mode. The fast 1.6Msps

throughput with no cycle latency makes the LTC2369-18

ideally suited for a wide variety of high speed applications.

An internal oscillator sets the conversion time, easing exter-

nal timing considerations. The LTC2369-18 automatically

powers down between conversions, leading to reduced

power dissipation that scales with the sampling rate.

32k Point FFT f

= 1.6Msps, f

= 2kHz

APPLICATIONS

1.6Msps Throughput Rate

±2.5LSB INL (Max)

Guaranteed 18-Bit No Missing Codes

Low Power: 18mW at 1.6Msps, 18μW at 1.6ksps

96.5dB SNR (Typ) at f

= 2kHz

–120dB THD (Typ) at f

= 2kHz

Guaranteed Operation to 125°C

2.5V Supply

Pseudo-Differential Unipolar Input Range: 0V to V

REF

Input Range from 2.5V to 5.1V

No Pipeline Delay, No Cycle Latency

1.8V to 5V I/O Voltages

SPI-Compatible Serial I/O with Daisy-Chain Mode

Internal Conversion Clock

16-Lead MSOP and 4mm × 3mm DFN Packages

Medical Imaging

High Speed Data Acquisition

Portable or Compact Instrumentation

Industrial Process Control

Low Power Battery-Operated Instrumentation

ATE

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the

property of their respective owners.

Protected by U.S. Patents including 7705765.

5.1Ω

REF

10nF

–

SAMPLE CLOCK

236918 TA01a

10μF 0.1μF

2.5V

REF

1.8V TO 5V

2.5V TO 5.1V

47μF

(X5R, 0805 SIZE)

REF GND

CHAIN

RDL/SDI

SDO

SCK

BUSY

CNV

LTC2369-18

6202

–

FREQUENCY (kHz)

0 100 200 300 400 800700600500

–180

AMPLITUDE (dBFS)

–60

–40

–20

–80

–100

–120

–140

–160

236918 TA01b

SNR = 96.5dB

THD = –127dB

SINAD = 96.5dB

SFDR = 134dB

Summary of content (24 pages)

PAGE 1
LTC2369-18 18-Bit, 1.6Msps, PseudoDifferential Unipolar SAR ADC with 96.5dB SNR FEATURES DESCRIPTION n The LTC®2369-18 is a low noise, low power, high speed 18-bit successive approximation register (SAR) ADC. Operating from a 2.5V supply, the LTC2369-18 has a 0V to VREF pseudo-differential unipolar input range with VREF ranging from 2.5V to 5.1V. The LTC2369-18 consumes only 18mW and achieves ±2.5LSB INL maximum, no missing codes at 18 bits with 96.5dB SNR. n n n n n n n n n n n n n n 1.
PAGE 2
LTC2369-18 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) Supply Voltage (VDD) ...............................................2.8V Supply Voltage (OVDD) ................................................6V Reference Input (REF).................................................6V Analog Input Voltage (Note 3) IN+, IN– .........................(GND – 0.3V) to (REF + 0.3V) Digital Input Voltage (Note 3) .......................... (GND – 0.3V) to (OVDD + 0.3V) Digital Output Voltage (Note 3) ..........................
PAGE 3
LTC2369-18 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS VIN+ Absolute Input Range (IN+) MIN TYP MAX UNITS (Note 5) l –0.
PAGE 4
LTC2369-18 REFERENCE INPUT The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS VREF Reference Voltage (Note 5) l MIN IREF Reference Input Current (Note 9) l TYP 2.5 0.85 MAX UNITS 5.1 V 1.1 mA DIGITAL INPUTS AND DIGITAL OUTPUTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
PAGE 5
LTC2369-18 ADC TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER tSCKL SCK Low Time CONDITIONS tSSDISCK SDI Setup Time From SCK↑ tHSDISCK tSCKCH tDSDO MIN TYP MAX UNITS l 4 ns (Note 11) l 4 ns SDI Hold Time From SCK↑ (Note 11) l 1 ns SCK Period in Chain Mode tSCKCH = tSSDISCK + tDSDO (Note 11) l 13.
PAGE 6
LTC2369-18 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VDD = 2.5V, OVDD = 2.5V, REF = 5V, fSMPL = 1.6Msps, unless otherwise noted. Integral Nonlinearity vs Output Code Differential Nonlinearity vs Output Code DC Histogram 0.5 2.0 40000 0.4 1.5 X = 1.3 35000 0.3 0.5 0.0 –0.5 –1.0 30000 0.2 0.1 COUNTS DNL ERROR (LSB) INL ERROR (LSB) 1.0 0.0 –0.1 20000 15000 –0.2 10000 –0.3 –1.5 25000 5000 –0.4 –0.5 –2.
PAGE 7
LTC2369-18 TYPICAL PERFORMANCE CHARACTERISTICS fSMPL = 1.6Msps, unless otherwise noted. THD, Harmonics vs Temperature, fIN = 2kHz –110 97.5 –115 97.0 SNR 96.5 SINAD 96.0 95.5 95.0 –120 THD –125 2ND –130 3RD –135 94.0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) –145 –55 –35 –15 0 MIN DNL –0.
PAGE 8
LTC2369-18 PIN FUNCTIONS CHAIN (Pin 1): Chain Mode Selector Pin. When low, the LTC2369-18 operates in normal mode and the RDL/SDI input pin functions to enable or disable SDO. When high, the LTC2369-18 operates in chain mode and the RDL/SDI pin functions as SDI, the daisy-chain serial data input. Logic levels are determined by OVDD. VDD (Pin 2): 2.5V Power Supply. The range of VDD is 2.375V to 2.625V. Bypass VDD to GND with a 10μF ceramic capacitor. GND (Pins 3, 6, 10 and 16): Ground.
PAGE 9
LTC2369-18 FUNCTIONAL BLOCK DIAGRAM VDD = 2.5V OVDD = 1.
PAGE 10
LTC2369-18 APPLICATIONS INFORMATION OVERVIEW Fast 1.6Msps throughput with no cycle latency makes the LTC2369-18 ideally suited for a wide variety of high speed applications. An internal oscillator sets the conversion time, easing external timing considerations. The LTC2369-18 dissipates only 18mW at 1.6Msps, while an auto power-down feature is provided to further reduce power dissipation during inactive periods. CONVERTER OPERATION The LTC2369-18 operates in two phases.
PAGE 11
LTC2369-18 APPLICATIONS INFORMATION INPUT DRIVE CIRCUITS A low impedance source can directly drive the high impedance input of the LTC2369-18 without gain error. A high impedance source should be buffered to minimize settling time during acquisition and to optimize the distortion performance of the ADC. Minimizing settling time is important even for DC inputs, because the ADC input draws a current spike when entering acquisition.
PAGE 12
LTC2369-18 APPLICATIONS INFORMATION VCM = VREF/2 200pF R2 499Ω R4 402Ω ADC REFERENCE + 3 R3 2k 10μF 5V LT6202 0V – 4 RIN 2k 10V 0V –10V 1 R1 499Ω 200pF 236918 F05a Figure 5a. LT6202 Converting a ±10V Bipolar Signal to a 0V to 5V Input Signal 0 SNR = 96.1dB THD = –97.3dB SINAD = 92.7dB SFDR = 97.5dB –20 AMPLITUDE (dBFS) –40 –60 The REF pin of the LTC2369-18 draws charge (QCONV) from the 47μF bypass capacitor during each conversion cycle.
PAGE 13
LTC2369-18 APPLICATIONS INFORMATION In applications where power management is critical and the external reference may be powered down, it is recommended that REF is kept greater than 2V in order to guarantee a maximum shutdown current of 140μA. In such applications, a Schottky diode can be placed between REF and VDD, as shown in Figure 7. REF VDD the RMS amplitude of all other frequency components except the first five harmonics and DC. Figure 8 shows that the LTC2369-18 achieves a typical SNR of 96.
PAGE 14
LTC2369-18 APPLICATIONS INFORMATION The LTC2369-18 does not have any specific power supply sequencing requirements. Care should be taken to adhere to the maximum voltage relationships described in the Absolute Maximum Ratings section. The LTC2369-18 has a power-on-reset (POR) circuit that will reset the LTC2369-18 at initial power-up or whenever the power supply voltage drops below 1V. Once the supply voltage re-enters the nominal supply voltage range, the POR will reinitialize the ADC.
PAGE 15
LTC2369-18 TIMING DIAGRAMS Normal Mode, Single Device Figure 10 shows a single LTC2369-18 operated in normal mode with CHAIN and RDL/SDI tied to ground. With RDL/SDI grounded, SDO is enabled and the MSB(D17) of the new conversion data is available at the falling edge of BUSY. This is the simplest way to operate the LTC2369-18. When CHAIN = 0, the LTC2369-18 operates in normal mode. In normal mode, RDL/SDI enables or disables the serial data output pin SDO. If RDL/SDI is high, SDO is in high impedance.
PAGE 16
LTC2369-18 TIMING DIAGRAMS Normal Mode, Multiple Devices be used to allow only one LTC2369-18 to drive SDO at a time in order to avoid bus conflicts. As shown in Figure 11, the RDL/SDI inputs idle high and are individually brought low to read data out of each device between conversions. When RDL/SDI is brought low, the MSB of the selected device is output onto SDO. Figure 11 shows multiple LTC2369-18 devices operating in normal mode (CHAIN = 0) sharing CNV, SCK and SDO.
PAGE 17
LTC2369-18 TIMING DIAGRAMS Chain Mode, Multiple Devices number of converters. Figure 12 shows an example with two daisy-chained devices. The MSB of converter A will appear at SDO of converter B after 18 SCK cycles. The MSB of converter A is clocked in at the SDI/RDL pin of converter B on the rising edge of the first SCK. When CHAIN = OVDD, the LTC2369-18 operates in chain mode.
PAGE 18
LTC2369-18 BOARD LAYOUT To obtain the best performance from the LTC2369-18 a printed circuit board is recommended. Layout for the printed circuit board (PCB) should ensure the digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital clocks or signals alongside analog signals or underneath the ADC. Recommended Layout The following is an example of a recommended PCB layout. A single solid ground plane is used.
PAGE 19
LTC2369-18 BOARD LAYOUT Partial Layer 1 Component Side Partial Layer 2 Ground Plane 236918fa 19
PAGE 20
LTC2369-18 BOARD LAYOUT Partial Layer 3 PWR Plane Partial Layer 4 Bottom Layer 236918fa 20
PAGE 21
AIN – J8 E7 EXT VREF/2 R39 0Ω JP5 HD1X3-100 EXT_CM J4 AIN+ R14 0Ω COUPLING AC DC C46 1μF 3 2 1 C8 1μF +2.5V R15 OPT HD1X3-100 JP2 CM C18 OPT C17 10μF JP1 HD1X3-100 C47 OPT C48 10μF 6.3V 4 2 5 4 +3.3V C2 0.1μF R3 CLK 33Ω TO CPLD R41 OPT R40 OPT R9 OPT C49 OPT C63 10μF 6.3V 5 V+ 2 C44 1μF C59 1μF V+ 4 OUT1 1 U15 LT6202CS5 C57 0.1μF V– C43 0.1μF C55 1μF 3 +IN1 V– C61 10μF 6.
PAGE 22
LTC2369-18 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. DE Package 16-Lead Plastic DFN (4mm × 3mm) (Reference LTC DWG # 05-08-1732 Rev Ø) R = 0.115 TYP 4.00 ±0.10 (2 SIDES) R = 0.05 TYP 0.70 ±0.05 3.30 ±0.05 3.60 ±0.05 2.20 ±0.05 9 3.30 ±0.10 3.00 ±0.10 (2 SIDES) 1.70 ± 0.05 PACKAGE OUTLINE 0.40 ± 0.10 16 1.70 ± 0.10 PIN 1 NOTCH R = 0.20 OR 0.35 × 45° CHAMFER PIN 1 TOP MARK (SEE NOTE 6) (DE16) DFN 0806 REV Ø 8 0.75 ±0.
PAGE 23
LTC2369-18 REVISION HISTORY REV DATE DESCRIPTION A 03/12 Updated conditions for IPD and PD in Power Requirements section PAGE NUMBER 4 Added Figure 7 and associated text 13 236918fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PAGE 24
LTC2369-18 TYPICAL APPLICATION LT6202 Converting a ±10V Bipolar Signal to a 0V to 5V Input Signal Into the LTC2369-18 LTC6655-5 VIN VOUT_F VOUT_S 8V 5V 200pF 47μF R2 3k 5 V+ R4 402Ω 3 10μF LT6202 2.5V 5V + 0V 5.