Datasheet

ManualsBrandsLINEAR TECHNOLOGY ManualsData collecting ICsData acquisition IC - AD converter (ADC) External DFN 16

LTC2377-20

237720f

For more information www.linear.com/LTC2377-20

Typical applicaTion

FeaTures DescripTion

20-Bit, 500ksps, Low Power

SAR ADC with 0.5ppm INL

The LTC

2377-20 is a low noise, low power, high speed

20-bit successive approximation register (SAR) ADC. Op-

erating from a 2.5V supply, the LTC2377-20 has a ±V

REF

fully differential input range with V

REF

ranging from 2.5V

to 5.1V. The LTC2377-20 consumes only 10.5mW and

achieves ±2ppm INL maximum, no missing codes at 20

bits with 104dB SNR.

The LTC2377-20 has a high speed SPI-compatible serial

interface that supports 1.8V, 2.5V, 3.3V and 5V logic

while also featuring a daisy-chain mode. The fast 500ksps

throughput with no cycle latency makes the LTC2377-20

ideally suited for a wide variety of high speed applications.

An internal oscillator sets the conversion time, easing exter-

nal timing considerations. The LTC2377-20 automatically

powers down between conversions, leading to reduced

power dissipation that scales with the sampling rate.

The LTC2377-20 features a unique digital gain compres-

sion (DGC) function, which eliminates the driver amplifier’s

negative supply while preserving the full resolution of the

ADC. When enabled, the ADC performs a digital scaling

function that maps zero-scale code from 0V to 0.1 • V

REF

and full-scale code from V

REF

to 0.9 • V

REF

. For a typical

reference voltage of 5V, the full-scale input range is now

0.5V to 4.5V, which provides adequate headroom for

powering the driving amplifier from a single 5.5V supply.

Integral Nonlinearity vs Output Code

applicaTions

500ksps Throughput Rate

±0.5ppm INL (Typ)

Guaranteed 20-Bit No Missing Codes

Low Power: 10.5mW at 500ksps, 10.5µW at 500sps

104dB SNR (Typ) at f

= 2kHz

–125dB THD (Typ) at f

= 2kHz

Digital Gain Compression (DGC)

Guaranteed Operation to 85°C

2.5V Supply

Fully Differential Input Range ±V

REF

Input Range from 2.5V to 5.1V

No Pipeline Delay, No Cycle Latency

1.8V to 5V I/O Voltages

SPI-Compatible Serial I/O with Daisy-Chain Mode

Internal Conversion Clock

16-Lead MSOP and 4mm × 3mm DFN Packages

Medical Imaging

High Speed Data Acquisition

Portable or Compact Instrumentation

Industrial Process Control

Low Power Battery-Operated Instrumentation

ATE

OUTPUT CODE

0 262144 524288 786432 1048576

–2.0

INL ERROR (ppm)

0.5

1.0

1.5

–0.5

–1.0

–1.5

2.0

237720 TA02

10Ω

REF

10Ω

3300pF

6800pF

–

REF

SAMPLE CLOCK

237720 TA01

10µF 0.1µF

2.5V

REF

1.8V TO 5V

2.5V TO 5.1V

47µF

(X7R, 1210 SIZE)

REF GND

CHAIN

RDL/SDI

SDO

SCK

BUSY

CNV

REF/DGC

LTC2377-20

–

L, LT, LT C , LTM , Linear Technology and the Linear logo are registered trademarks and

SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the

property of their respective owners.

Patents Pending. Protected by U.S. Patents, including

7705765, 7961132, 8319673.

Summary of content (28 pages)

PAGE 1
LTC2377-20 20-Bit, 500ksps, Low Power SAR ADC with 0.5ppm INL Description Features n n n n n n n n n n n n n n n n 500ksps Throughput Rate ±0.5ppm INL (Typ) Guaranteed 20-Bit No Missing Codes Low Power: 10.5mW at 500ksps, 10.5µW at 500sps 104dB SNR (Typ) at fIN = 2kHz –125dB THD (Typ) at fIN = 2kHz Digital Gain Compression (DGC) Guaranteed Operation to 85°C 2.5V Supply Fully Differential Input Range ±VREF VREF Input Range from 2.5V to 5.1V No Pipeline Delay, No Cycle Latency 1.
PAGE 2
LTC2377-20 Absolute Maximum Ratings (Notes 1, 2) Supply Voltage (VDD)................................................2.8V Supply Voltage (OVDD).................................................6V Reference Input (REF)..................................................6V Analog Input Voltage (Note 3) IN+, IN–..........................(GND – 0.3V) to (REF + 0.3V) REF/DGC Input (Note 3).....(GND – 0.3V) to (REF + 0.3V) Digital Input Voltage (Note 3)........................... (GND – 0.3V) to (OVDD + 0.
PAGE 3
LTC2377-20 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
PAGE 4
LTC2377-20 Reference Input The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS VREF Reference Voltage (Note 5) l MIN IREF Reference Input Current (Note 9) l VIHDGC High Level Input Voltage REF/DGC Pin l VILDGC Low Level Input Voltage REF/DGC Pin l TYP 2.5 0.47 MAX UNITS 5.1 V 0.53 mA 0.8VREF V 0.
PAGE 5
LTC2377-20 ADC timing characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER tSCKH SCK High Time CONDITIONS l 4 ns tSCKL SCK Low Time l 4 ns tSSDISCK SDI Setup Time From SCK↑ (Note 11) l 4 ns tHSDISCK SDI Hold Time From SCK↑ (Note 11) l 1 ns tSCKCH SCK Period in Chain Mode tSCKCH = tSSDISCK + tDSDO (Note 11) l 13.
PAGE 6
LTC2377-20 Typical Performance Characteristics REF = 5V, fSMPL = 500ksps, unless otherwise noted. Integral Nonlinearity vs Output Code Differential Nonlinearity vs Output Code 50000 1.5 0.4 45000 0.3 40000 0.2 35000 0.1 30000 0.5 0 –0.5 COUNTS 0.5 DNL ERROR (ppm) 0.0 –0.1 20000 –0.2 15000 –0.3 10000 –1.5 –0.4 5000 –2.0 –0.5 –1.
PAGE 7
LTC2377-20 Typical Performance Characteristics REF = 5V, fSMPL = 500ksps, unless otherwise noted. 106 SNR, SINAD vs Temperature, fIN = 2kHz –120 TA = 25°C, VDD = 2.5V, OVDD = 2.5V, VCM = 2.5V, THD, Harmonics vs Temperature, fIN = 2kHz INL vs Temperature 2.0 1.5 105 SINAD 103 102 –125 1.0 INL ERROR (ppm) HARMONICS, THD (dBFS) SNR, SINAD (dBFS) SNR 104 THD –130 3RD –135 0 MIN INL –0.5 –1.
PAGE 8
LTC2377-20 Pin Functions CHAIN (Pin 1): Chain Mode Selector Pin. When low, the LTC2377-20 operates in normal mode and the RDL/SDI input pin functions to enable or disable SDO. When high, the LTC2377-20 operates in chain mode and the RDL/SDI pin functions as SDI, the daisy-chain serial data input. Logic levels are determined by OVDD. BUSY (Pin 11): BUSY Indicator. Goes high at the start of a new conversion and returns low when the conversion has finished. Logic levels are determined by OVDD.
PAGE 9
LTC2377-20 Timing Diagram Conversion Timing Using the Serial Interface CHAIN, RDL/SDI = 0 CNV BUSY CONVERT HOLD POWER-DOWN ACQUIRE SCK D19 D18 D17 SDO D2 D1 D0 237720 TD01 Applications Information OVERVIEW CONVERTER OPERATION The LTC2377-20 is a low noise, low power, high speed 20-bit successive approximation register (SAR) ADC. Operating from a single 2.5V supply, the LTC2377-20 supports a large and flexible ±VREF fully differential input range with VREF ranging from 2.5V to 5.
PAGE 10
LTC2377-20 OUTPUT CODE (TWO’S COMPLEMENT) Applications Information tling of the analog signal during the acquisition phase. It also provides isolation between the signal source and the ADC input currents. 011...111 BIPOLAR ZERO 011...110 000...001 Noise and Distortion 000...000 111...111 111...110 100...001 FSR = +FS – –FS 1LSB = FSR/1048576 ≈ 1ppm 100...
PAGE 11
LTC2377-20 Applications Information Fully Settled – This case is characterized by filter time constants and an overall settling time that is considerably shorter than the sample period. When acquisition begins, the coupling filter is disturbed. For a typical first order RC filter, the disturbance will look like an initial step with an exponential decay. The amplifier will have its own response to the disturbance, which may include ringing.
PAGE 12
LTC2377-20 Applications Information IL1 + VE – RS2 Single-Ended-to-Differential Conversion IN+ LTC2377-20 IN– IL2 237720 F07 Figure 7. Source Impedances of a Driver and Input Leakage Currents of the LTC2377-20 ing temperature range and common mode input voltage range. Thus, any reasonable mismatch (below 5%) of the source impedances RS1 and RS2 will cause only a negligible error.
PAGE 13
LTC2377-20 Applications Information Digital Gain Compression The LTC2377-20 offers a digital gain compression (DGC) feature which defines the full-scale input swing to be between 10% and 90% of the ±VREF analog input range. To enable digital gain compression, bring the REF/DGC pin low. This feature allows the SAR ADC driver to be powered off of a single positive supply since each input swings between 0.5V and 4.5V as shown in Figure 10.
PAGE 14
LTC2377-20 Applications Information 1ppm linearity may require that the offset is known to vary less than 5μV for a 5V swing. However, greater offset variations may be acceptable if the relationship is known to be (mostly) linear. Unity-gain buffer amplifiers typically require substantial headroom to the power supply rails for best performance.
PAGE 15
LTC2377-20 Applications Information Signal-to-Noise Ratio (SNR) Power Supply Sequencing The signal-to-noise ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components except the first five harmonics and DC. Figure 13 shows that the LTC2377-20 achieves a typical SNR of 104dB at a 500kHz sampling rate with a 2kHz input. The LTC2377-20 does not have any specific power supply sequencing requirements.
PAGE 16
LTC2377-20 Applications Information Auto Power-Down DIGITAL INTERFACE The LTC2377-20 automatically powers down after a conversion has been completed and powers up once a new conversion is initiated on the rising edge of CNV. During power down, data from the last conversion can be clocked out. To minimize power dissipation during power down, disable SDO and turn off SCK. The auto power-down feature will reduce the power dissipation of the LTC2377-20 as the sampling frequency is reduced.
PAGE 17
LTC2377-20 Timing Diagrams Normal Mode, Single Device Figure 15 shows a single LTC2377-20 operated in normal mode with CHAIN and RDL/SDI tied to ground. With RDL/ SDI grounded, SDO is enabled and the MSB(D19) of the new conversion data is available at the falling edge of BUSY. This is the simplest way to operate the LTC2377-20. When CHAIN = 0, the LTC2377-20 operates in normal mode. In normal mode, RDL/SDI enables or disables the serial data output pin SDO. If RDL/SDI is high, SDO is in high impedance.
PAGE 18
LTC2377-20 timing diagrams Normal Mode, Multiple Devices Since SDO is shared, the RDL/SDI input of each ADC must be used to allow only one LTC2377-20 to drive SDO at a time in order to avoid bus conflicts. As shown in Figure 16, the RDL/SDI inputs idle high and are individually brought low to read data out of each device between conversions. When RDL/SDI is brought low, the MSB of the selected device is output onto SDO.
PAGE 19
LTC2377-20 timing diagrams Chain Mode, Multiple Devices This is useful for applications where hardware constraints may limit the number of lines needed to interface to a large number of converters. Figure 17 shows an example with two daisy-chained devices. The MSB of converter A will appear at SDO of converter B after 20 SCK cycles. The MSB of converter A is clocked in at the SDI/RDL pin of converter B on the rising edge of the first SCK. When CHAIN = OVDD, the LTC2377-20 operates in chain mode.
PAGE 20
LTC2377-20 Board Layout To obtain the best performance from the LTC2377-20 a printed circuit board is recommended. Layout for the printed circuit board (PCB) should ensure the digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital clocks or signals alongside analog signals or underneath the ADC. Recommended Layout The following is an example of a recommended PCB layout. A single solid ground plane is used.
PAGE 21
LTC2377-20 board layout Layer 1 Component Side 237720f For more information www.linear.
PAGE 22
LTC2377-20 board layout Layer 2 Ground Plane 237720f 22 For more information www.linear.
PAGE 23
LTC2377-20 board layout Layer 3 PWR Plane 237720f For more information www.linear.
PAGE 24
LTC2377-20 board layout Layer 4 Bottom Layer 237720f 24 For more information www.linear.
PAGE 25
C78 4.7µF 6.3V VREF R87 499k R86 499k 2 3 V– 4 5 V+ C45 0.1µF 25V C67 OPT C18 10µF 6.3V 1 R55 0Ω R54 OPT AC EXT_CM R88 1Ω JP8 COUPLING C77 0.1µF 25V U5 LT6202CS8 R53 0Ω J2 BNC AIN – 0 – VREF – + AIN+ 0 – VREF J4 BNC AC 1 DC E5 C8 1µF DC EXT C60 10µF 6.3V R56 OPT C59 10µF 6.3V C74 1µF 25V JP4 CM R18 249Ω C68 15pF COG VREF/2 C70 OPT C69 10µF 6.3V 1 3 JP7 COUPLING 2 2 3 2 1 For more information www.linear.com/LTC2377-20 2 4 C48 0.
PAGE 26
LTC2377-20 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. DE Package 16-Lead Plastic DFN (4mm × 3mm) (Reference LTC DWG # 05-08-1732 Rev Ø) 4.00 ±0.10 (2 SIDES) R = 0.05 TYP 0.70 ±0.05 3.60 ±0.05 2.20 ±0.05 3.30 ±0.05 1.70 ±0.05 PACKAGE OUTLINE PIN 1 TOP MARK (SEE NOTE 6) 9 R = 0.115 TYP 3.30 ±0.10 3.00 ±0.10 (2 SIDES) 1.70 ±0.10 0.200 REF PIN 1 NOTCH R = 0.20 OR 0.35 × 45° CHAMFER (DE16) DFN 0806 REV Ø 8 0.25 ±0.05 0.
PAGE 27
LTC2377-20 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. MS Package 16-Lead Plastic MSOP (Reference LTC DWG # 05-08-1669 Rev Ø) 4.039 ±0.102 (.159 ±.004) (NOTE 3) 0.889 ±0.127 (.035 ±.005) 5.23 (.206) MIN 16151413121110 9 3.20 – 3.45 (.126 – .136) 0.254 (.010) DETAIL “A” 3.00 ±0.102 (.118 ±.004) (NOTE 4) 4.90 ±0.152 (.193 ±.006) 0° – 6° TYP 0.280 ±0.076 (.011 ±.003) REF GAUGE PLANE 0.305 ±0.038 (.0120 ±.0015) TYP 0.
PAGE 28
LTC2377-20 Typical Application LTC6362 Configured to Accept a ±3.28V Input Signal While Running from a Single 5V Supply with Digital Gain Compression Enabled in the LTC2377-20 VIN LTC6655-4.096 5V VOUT_F 4.096V VOUT_S 1k 1k V+ 1k 3.28V 0V –3.28V 47µF 1k VCM 10µF 8 + 1 – 3 4 LTC6362 1k 2.5V 6800pF 0.41V IN+ 35.7Ω V– 6 1k IN– 35.7Ω 3.69V REF VDD LTC2377-20 3300pF 5 2 VCM 3.69V 6800pF REF/DGC 237720 TA03 0.