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LTC2380-16

238016fa

TYPICAL APPLICATION

FEATURES DESCRIPTION

16-Bit, 2Msps, Low Power

SAR ADC with 96.2dB SNR

The LTC

2380-16 is a low noise, low power, high speed

16-bit successive approximation register (SAR) ADC.

Operating from a 2.5V supply, the LTC2380-16 has a

±V

REF

fully differential input range with V

REF

ranging from

2.5V to 5.1V. The LTC2380-16 consumes only 19mW and

achieves ±0.6LSB INL maximum, no missing codes at

16 bits with 96.2dB SNR.

The LTC2380-16 has a high speed SPI-compatible serial

interface that supports 1.8V, 2.5V, 3.3V and 5V logic while

also featuring a daisy-chain mode. The fast 2Msps through-

put with no cycle latency makes the LTC2380-16 ideally

suited for a wide variety of high speed applications. An

internal oscillator sets the conversion time, easing external

timing considerations. The LTC2380-16 automatically pow-

ers down between conversions, leading to reduced power

dissipation that scales with the sampling rate.

The LTC2380-16 features a unique digital gain compres-

sion (DGC) function, which eliminates the driver amplifier’s

negative supply while preserving the full resolution of the

ADC. When enabled, the ADC performs a digital scaling

function that maps zero-scale code from 0V to 0.1 • V

REF

and full-scale code from V

REF

to 0.9 • V

REF

. For a typical

reference voltage of 5V, the full-scale input range is now

0.5V to 4.5V, which provides adequate headroom for

powering the driving amplifier from a single 5.5V supply.

32k Point FFT f

= 2Msps, f

= 2kHz

APPLICATIONS

2Msps Throughput Rate

±0.6LSB INL (Max)

Guaranteed 16-Bit No Missing Codes

Low Power: 19mW at 2Msps, 19μW at 2ksps

96.2dB SNR (typ) at f

= 2kHz

–117dB THD (typ) at f

= 2kHz

Digital Gain Compression (DGC)

Guaranteed Operation to 125°C

2.5V Supply

Fully Differential Input Range ±V

REF

Input Range from 2.5V to 5.1V

No Pipeline Delay, No Cycle Latency

1.8V to 5V I/O Voltages

SPI-Compatible Serial I/O with Daisy-Chain Mode

Internal Conversion Clock

16-Lead MSOP and 4mm × 3mm DFN Packages

Medical Imaging

High Speed Data Acquisition

Portable or Compact Instrumentation

Industrial Process Control

Low Power Battery-Operated Instrumentation

ATE

FREQUENCY (kHz)

0 100 200 300 400 1000900800700600500

–180

AMPLITUDE (dBFS)

–60

–40

–20

–80

–100

–120

–140

–160

238016 TA02

SNR = 96.4dB

THD = –119dB

SINAD = 96.3dB

SFDR = 122dB

REF

20

REF

20

3300pF

SAMPLE CLOCK

238016 TA01

10µF 0.1µF

2.5V

REF

1.8V TO 5V

2.5V TO 5.1V

47µF

(X5R, 0805 SIZE)

REF GND

CHAIN

RDL/SDI

SDO

SCK

BUSY

CNV

REF/DGC

LTC2380-16

–

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the property

of their respective owners. Protected by U.S. Patents including 7705765.

Summary of content (26 pages)

PAGE 1
LTC2380-16 16-Bit, 2Msps, Low Power SAR ADC with 96.2dB SNR FEATURES DESCRIPTION n The LTC®2380-16 is a low noise, low power, high speed 16-bit successive approximation register (SAR) ADC. Operating from a 2.5V supply, the LTC2380-16 has a ±VREF fully differential input range with VREF ranging from 2.5V to 5.1V. The LTC2380-16 consumes only 19mW and achieves ±0.6LSB INL maximum, no missing codes at 16 bits with 96.2dB SNR. n n n n n n n n n n n n n n n 2Msps Throughput Rate ±0.
PAGE 2
LTC2380-16 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) Supply Voltage (VDD) ...............................................2.8V Supply Voltage (OVDD) ................................................6V Reference Input (REF).................................................6V Analog Input Voltage (Note 3) IN+, IN– ......................... (GND –0.3V) to (REF + 0.3V) REF/DGC Input (Note 3) .... (GND –0.3V) to (REF + 0.3V) Digital Input Voltage (Note 3) ........................... (GND –0.3V) to (OVDD + 0.
PAGE 3
LTC2380-16 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS VIN+ Absolute Input Range (IN+) MIN (Note 5) l VIN – Absolute Input Range (IN–) (Note 5) VIN+ – VIN– Input Differential Voltage Range VIN = VIN+ – VIN– VCM TYP MAX UNITS –0.05 VREF + 0.05 l –0.05 VREF + 0.05 V l –VREF +VREF V Common-Mode Input Range l VREF/2– 0.1 VREF/2+ 0.
PAGE 4
LTC2380-16 REFERENCE INPUT The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS VREF Reference Voltage (Note 5) l MIN IREF Reference Input Current (Note 9) l VIHDGC High Level Input Voltage REF/DGC Pin l VILDGC Low Level Input Voltage REF/DGC Pin l TYP 2.5 1.2 MAX UNITS 5.1 V 1.4 mA 0.8VREF V 0.
PAGE 5
LTC2380-16 ADC TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER tSCKL SCK Low Time CONDITIONS tSSDISCK SDI Setup Time From SCK↑ tHSDISCK tSCKCH tDSDO MIN TYP MAX UNITS l 4 ns (Note 11) l 4 ns SDI Hold Time From SCK↑ (Note 11) l 1 ns SCK Period in Chain Mode tSCKCH = tSSDISCK + tDSDO (Note 11) l 13.
PAGE 6
LTC2380-16 TYPICAL PERFORMANCE CHARACTERISTICS REF = 5V, fSMPL = 2Msps, unless otherwise noted. Differential Nonlinearity vs Output Code 1.0 0.5 0.8 0.4 0.6 0.3 0.4 0.2 0.2 0.0 –0.2 –0.4 100000 0.0 –0.1 –0.2 –0.3 –0.8 –0.
PAGE 7
LTC2380-16 TYPICAL PERFORMANCE CHARACTERISTICS REF = 5V, fSMPL = 2Msps, unless otherwise noted. SNR, SINAD vs Temperature, fIN = 2kHz THD, Harmonics vs Temperature, fIN = 2kHz 98.0 MAX INL SNR 96.5 SINAD 95.5 95.0 THD –115 3RD –120 –125 2ND –130 94.5 94.0 –55 –35 –15 –135 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) INL/DNL ERROR (LSB) HARMONICS, THD (dBFS) SNR, SINAD (dBFS) 0.50 –110 97.0 Full-Scale Error vs Temperature 0 –0.5 –1.0 –2.0 –55 –35 –15 –0.
PAGE 8
LTC2380-16 PIN FUNCTIONS CHAIN (Pin 1): Chain Mode Selector Pin. When low, the LTC2380-16 operates in normal mode and the RDL/SDI input pin functions to enable or disable SDO. When high, the LTC2380-16 operates in chain mode and the RDL/SDI pin functions as SDI, the daisy-chain serial data input. Logic levels are determined by 0VDD. BUSY (Pin 11): BUSY Indicator. Goes high at the start of a new conversion and returns low when the conversion has finished. Logic levels are determined by 0VDD.
PAGE 9
LTC2380-16 TIMING DIAGRAM Conversion Timing Using the Serial Interface CHAIN, RDL/SDI = 0 CNV POWER-DOWN AND ACQUIRE BUSY CONVERT SCK D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SDO 238016 TD02 238016fa 9
PAGE 10
LTC2380-16 APPLICATIONS INFORMATION TRANSFER FUNCTION The LTC2380-16 is a low noise, low power, high speed 16-bit successive approximation register (SAR) ADC. Operating from a single 2.5V supply, the LTC2380-16 supports a large and flexible ±VREF fully differential input range with VREF ranging from 2.5V to 5.1V, making it ideal for high performance applications which require a wide dynamic range. The LTC2380-16 achieves ±0.6LSB INL max, no missing codes at 16 bits and 96.2dB SNR.
PAGE 11
LTC2380-16 APPLICATIONS INFORMATION INPUT DRIVE CIRCUITS A low impedance source can directly drive the high impedance inputs of the LTC2380-16 without gain error. A high impedance source should be buffered to minimize settling time during acquisition and to optimize the distortion performance of the ADC. Minimizing settling time is important even for DC inputs, because the ADC inputs draw a current spike when entering acquisition.
PAGE 12
LTC2380-16 APPLICATIONS INFORMATION LT6350 4 5V 8 0V 1 + – RINT RINT 2 + – 5 OUT2 0V –40 5V 4 8 10μF R4 = 402 R3 = 2k VCM = VREF/2 + – RINT 1 10V 0V –10V RIN = 2k 2 R1 = 499 + – OUT1 RINT 0V 5V – + 5 OUT2 0V VCM = VREF/2 220pF 238016 F06a Figure 6a. LT6350 Converting a ±10V Single-Ended Signal to a ±5V Differential Input Signal SNR = 96.1dB THD = –104.7dB SINAD = 95.5dB SFDR = 108dB –20 LT6350 5V – + Figure 5a.
PAGE 13
LTC2380-16 APPLICATIONS INFORMATION many applications. With its small size, low power and high accuracy, the LTC6655-5 is particularly well suited for use with the LTC2380-16. The LTC6655-5 offers 0.025% (max) initial accuracy and 2ppm/°C (max) temperature coefficient for high precision applications. The LTC6655-5 is fully specified over the H-grade temperature range and complements the extended temperature operation of the LTC2380-16 up to 125°C.
PAGE 14
LTC2380-16 APPLICATIONS INFORMATION 0μA to a maximum of 1.4mA at 2Msps. This step in DC current draw triggers a transient response in the reference that must be considered since any deviation in the reference output voltage will affect the accuracy of the output code. In applications where the transient response of the reference is important, the fast settling LTC6655-5 reference is also recommended.
PAGE 15
LTC2380-16 APPLICATIONS INFORMATION reinitialize the ADC. No conversions should be initiated until 20μs after a POR event to ensure the reinitialization period has ended. Any conversions initiated before this time will produce invalid results. powered-down for a larger fraction of the conversion cycle (tCYC) at lower sample rates, thereby reducing the average power dissipation which scales with the sampling rate as shown in Figure 12.
PAGE 16
LTC2380-16 TIMING DIAGRAMS Normal Mode, Single Device Figure 13 shows a single LTC2380-16 operated in normal mode with CHAIN and RDL/SDI tied to ground. With RDL/ SDI grounded, SDO is enabled and the MSB(D15) of the new conversion data is available at the falling edge of BUSY. This is the simplest way to operate the LTC2380-16. When CHAIN = 0, the LTC2380-16 operates in normal mode. In normal mode, RDL/SDI enables or disables the serial data output pin SDO. If RDL/SDI is high, SDO is in high impedance.
PAGE 17
LTC2380-16 TIMING DIAGRAMS Normal Mode, Multiple Devices Since SDO is shared, the RDL/SDI input of each ADC must be used to allow only one LTC2380-16 to drive SDO at a time in order to avoid bus conflicts. As shown in Figure 14, the RDL/SDI inputs idle high and are individually brought low to read data out of each device between conversions. When RDL/SDI is brought low, the MSB of the selected device is output onto SDO.
PAGE 18
LTC2380-16 TIMING DIAGRAMS Chain Mode, Multiple Devices This is useful for applications where hardware constraints may limit the number of lines needed to interface to a large number of converters. Figure 15 shows an example with two daisy-chained devices. The MSB of converter A will appear at SDO of converter B after 16 SCK cycles. The MSB of converter A is clocked in at the SDI/RDL pin of converter B on the rising edge of the first SCK. When CHAIN = OVDD, the LTC2380-16 operates in chain mode.
PAGE 19
LTC2380-16 BOARD LAYOUT To obtain the best performance from the LTC2380-16 a printed circuit board is recommended. Layout for the printed circuit board (PCB) should ensure the digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital clocks or signals alongside analog signals or underneath the ADC. Recommended Layout The following is an example of a recommended PCB layout. A single solid ground plane is used.
PAGE 20
LTC2380-16 BOARD LAYOUT Partial Layer 1 Component Side Partial Layer 2 Ground Plane 238016fa 20
PAGE 21
LTC2380-16 BOARD LAYOUT Partial Layer 3 PWR Plane Partial Layer 4 Bottom Layer 238016fa 21
PAGE 22
AIN – J8 E7 EXT VREF/2 R14 0Ω R39 0Ω JP5 HD1X3-100 EXT_CM AIN+ J4 COUPLING AC DC 3 2 1 C8 1μF +2.5V COUPLING AC DC C46 1μF C47 OPT C48 10μF 6.3V 5 4 +3.3V C1 0.1μF 2 5 4 +3.3V C2 0.1μF R3 CLK 33Ω TO CPLD R41 OPT R40 1k R18 1k R9 OPT C49 OPT 3 V+ C43 0.1μF C55 1μF 6 C45 V – 10μF 2 +IN2 8 +IN1 V– C63 10μF 6.3V C62 1μF R37 OPT R34 0Ω C61 10μF 6.3V C42 15pF R32 0Ω V+ C44 1μF C57 0.
PAGE 23
LTC2380-16 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. DE Package 16-Lead Plastic DFN (4mm × 3mm) (Reference LTC DWG # 05-08-1732 Rev Ø) R = 0.115 TYP 4.00 ±0.10 (2 SIDES) 0.70 ±0.05 3.60 ±0.05 2.20 ±0.05 PACKAGE OUTLINE PIN 1 TOP MARK (SEE NOTE 6) 3.30 ±0.10 3.00 ±0.10 (2 SIDES) 1.70 ± 0.10 3.15 REF RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.200 REF PIN 1 NOTCH R = 0.
PAGE 24
LTC2380-16 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. MS Package 16-Lead Plastic MSOP (Reference LTC DWG # 05-08-1669 Rev Ø) 4.039 p 0.102 (.159 p .004) (NOTE 3) 0.889 p 0.127 (.035 p .005) 5.23 (.206) MIN 16151413121110 9 3.20 – 3.45 (.126 – .136) 0.254 (.010) DETAIL “A” 0o – 6o TYP 0.280 p 0.076 (.011 p .003) REF 3.00 p 0.102 (.118 p .004) (NOTE 4) 4.90 p 0.152 (.193 p .006) GAUGE PLANE 0.305 p 0.038 (.0120 p .
PAGE 25
LTC2380-16 REVISION HISTORY REV DATE DESCRIPTION A 9/11 Updated θJA in DE Pin Configuration PAGE NUMBER 2 Updated specifications in Converter Characteristics and Dynamic Accuracy sections 3 Updated Figure 15 18 Updated Related Parts 24 238016fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use.
PAGE 26
LTC2380-16 TYPICAL APPLICATION LT6350 Configured to Accept a ±10V Input Signal While Running Off of a Single 5.5V Supply When Digital Gain Compression Is Enabled in the LTC2380-16 VIN 5.5V LTC6655-5 VOUT_F 5V VOUT_S 1k 47μF VCM 4.5V 1k 10μF V+ LT6350 6.04k 4 8 4.32k 10μF + – RIN = 15k OUT1 3300pF 0.5V IN+ 20Ω RINT RINT 2 – + IN– 20Ω 5 V– 3.01k OUT2 4.5V 6 REF VDD LTC2380-16 3300pF 1 10V 0V –10V 2.5V 3 3300pF REF/DGC 238016 TA03 0.