LTC2410 24-Bit No Latency ∆ΣTM ADC with Differential Input and Differential Reference DESCRIPTIO U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Differential Input and Differential Reference with GND to VCC Common Mode Range 2ppm INL, No Missing Codes 2.5ppm Full-Scale Error 0.1ppm Offset 0.
LTC2410 U W W W ABSOLUTE AXI U RATI GS U W U PACKAGE/ORDER I FOR ATIO (Notes 1, 2) Supply Voltage (VCC) to GND .......................– 0.3V to 7V Analog Input Pins Voltage to GND .................................... – 0.3V to (VCC + 0.3V) Reference Input Pins Voltage to GND .................................... – 0.3V to (VCC + 0.3V) Digital Input Voltage to GND ........ – 0.3V to (VCC + 0.3V) Digital Output Voltage to GND ..... – 0.3V to (VCC + 0.3V) Operating Temperature Range LTC2410C ...........
LTC2410 U CO VERTER CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4) PARAMETER CONDITIONS MIN TYP ● 130 140 ● 140 dB ● 140 dB (Note 7) ● 110 140 dB Input Normal Mode Rejection 50Hz ±2% (Note 8) ● 110 140 dB Reference Common Mode Rejection DC 2.5V ≤ REF+ ≤ VCC, GND ≤ REF– ≤ 2.5V, VREF = 2.5V, IN– = IN+ = GND ● 130 140 dB Power Supply Rejection, DC REF+ = 2.
LTC2410 U U DIGITAL I PUTS A D DIGITAL OUTPUTS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) SYMBOL PARAMETER CONDITIONS MIN VIH High Level Input Voltage CS, FO 2.7V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 3.3V ● VIL Low Level Input Voltage CS, FO 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V ● VIH High Level Input Voltage SCK 2.7V ≤ VCC ≤ 5.5V (Note 9) 2.7V ≤ VCC ≤ 3.3V (Note 9) ● VIL Low Level Input Voltage SCK 4.
LTC2410 UW TI I G CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
LTC2410 U W TYPICAL PERFOR A CE CHARACTERISTICS Total Unadjusted Error vs Temperature (VCC = 5V, VREF = 5V) Total Unadjusted Error vs Temperature (VCC = 5V, VREF = 2.5V) 1.5 1.0 TUE (ppm OF VREF) 0.5 0 –1.0 VCC = 5V REF + = 5V REF – = GND VREF = 5V VINCM = 2.5V FO = GND TA = 90°C 0 TA = –45°C TA = 90°C TA = 25°C –0.5 TA = 25°C TA = –45°C 1 1.5 2 –1.5 2.5 –0.5 0 VIN (V) 0.5 8 1.0 0 INL ERROR (ppm OF VREF) INL ERROR (ppm OF VREF) 10 TA = –45°C TA = 25°C TA = 90°C –0.5 –1.0 1.
LTC2410 U W TYPICAL PERFOR A CE CHARACTERISTICS 8 6 4 GAUSSIAN DISTRIBUTION m = 0.033ppm σ = 0.293ppm 12 2 10 8 6 4 10,000 CONSECUTIVE READINGS VCC = 5V VREF = 2.5V VIN = 0V REF + = 2.5V REF – = GND IN + = 1.25V IN – = 1.25V FO = 460800Hz TA = 25°C GAUSSIAN DISTRIBUTION m = 0.014ppm σ = 0.292ppm 2 0 –1.6 –0.8 0 0.8 OUTPUT CODE (ppm OF VREF) 0 –1.6 –1.2 –0.8 –0.4 0 0.4 0.8 1.2 OUTPUT CODE (ppm OF VREF) 1.6 8 6 4 6 4 GAUSSIAN DISTRIBUTION m = 0.079ppm σ = 0.
LTC2410 U W TYPICAL PERFOR A CE CHARACTERISTICS RMS Noise vs VINCM RMS Noise vs Temperature (TA) 850 825 800 800 775 VCC = 5V REF + = 5V REF – = GND VREF = 5V IN + = VINCM IN – = VINCM VIN = 0V FO = GND TA = 25°C 750 725 700 675 650 –0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VINCM (V) 850 VCC = 5V REF + = 5V REF – = GND IN + = 2.5V IN – = 2.5V VIN = 0V FO = GND 775 800 750 725 675 –25 0 25 50 TEMPERATURE (°C) 75 725 700 675 0 0.5 1 1.5 2 2.5 3 VREF (V) 3.5 4 4.5 0.3 0.2 0.2 0.
LTC2410 U W TYPICAL PERFOR A CE CHARACTERISTICS + Full-Scale Error vs VCC 2 1 0 REF + = 2.5V REF – = GND VREF = 2.5V IN + = 1.25V IN – = GND FO = GND TA = 25°C –1 –2 –3 2.7 3.1 3.5 3.9 4.3 VCC (V) 4.7 5.1 2 1 0 VCC = 5V REF + = VREF REF – = GND IN + = 0.5 • REF + IN – = GND FO = GND TA = 25°C –1 –2 –3 5.5 3 0 0.5 1 1.5 2 2.5 3 VREF (V) 3.5 4 2410 G28 – Full-Scale Error vs VCC 0 –1 –2 –3 2.7 3.1 3.5 3.9 4.3 VCC (V) 4.7 5.1 1 –40 –1 –60 –80 –2 –120 0 0.5 1 1.5 2 2.
LTC2410 U W TYPICAL PERFOR A CE CHARACTERISTICS SUPPLY CURRENT (µA) 210 FO = GND CS = GND SCK = NC SDO = NC 1100 900 VCC = 5.5V 200 190 VCC = 4.1V 180 VCC = 2.7V 800 700 600 500 22 400 21 20 VCC = 5.5V VCC = 4.1V 19 VCC = 2.
LTC2410 W FU CTIO AL BLOCK DIAGRA U U INTERNAL OSCILLATOR VCC GND IN + IN – AUTOCALIBRATION AND CONTROL + –∫ ∫ FO (INT/EXT) ∫ ∑ SDO SERIAL INTERFACE ADC SCK CS REF + REF – DECIMATING FIR – + DAC 2410 FD Figure 1. Functional Block Diagram TEST CIRCUITS VCC 1.69k SDO SDO 1.
LTC2410 U W U U APPLICATIO S I FOR ATIO Once CS is pulled LOW, the device begins outputting the conversion result. There is no latency in the conversion result. The data output corresponds to the conversion just performed. This result is shifted out on the serial data out pin (SDO) under the control of the serial clock (SCK). Data is updated on the falling edge of SCK allowing the user to reliably latch data on the rising edge of SCK (see Figure 3).
LTC2410 U W U U APPLICATIO S I FOR ATIO Input Voltage Range The analog input is truly differential with an absolute/ common mode range for the IN+ and IN– input pins extending from GND – 0.3V to VCC + 0.3V. Outside these limits, the ESD protection devices begin to turn on and the errors due to input leakage current increase rapidly. Within these limits, the LTC2410 converts the bipolar differential input signal, VIN = IN+ – IN–, from – FS = – 0.5 • VREF to +FS = 0.5 • VREF where VREF = REF+ – REF–.
LTC2410 U U W U APPLICATIO S I FOR ATIO on the rising edge of the 32nd SCK pulse. On the falling edge of the 32nd SCK pulse, SDO goes HIGH indicating the initiation of a new conversion cycle. This bit serves as EOC (Bit 31) for the next conversion cycle. Table 2 summarizes the output data format. As long as the voltage on the IN+ and IN– pins is maintained within the – 0.3V to (VCC + 0.
LTC2410 U W U U APPLICATIO S I FOR ATIO –80 synchronized with an outside source, the LTC2410 can operate with an external conversion clock. The converter automatically detects the presence of an external clock signal at the FO pin and turns off the internal oscillator. The frequency fEOSC of the external signal must be at least 2560Hz (1Hz notch frequency) to be detected.
LTC2410 U W U U APPLICATIO S I FOR ATIO Serial Clock Input/Output (SCK) described in the previous sections. The serial clock signal present on SCK (Pin 13) is used to synchronize the data transfer. Each bit of data is shifted out the SDO pin on the falling edge of the serial clock. In addition, the CS signal can be used to trigger a new conversion cycle before the entire serial data transfer has been completed.
LTC2410 U U W U APPLICATIO S I FOR ATIO As described above, CS may be pulled LOW at any time in order to monitor the conversion status. The serial clock mode is selected on the falling edge of CS. To select the external serial clock mode, the serial clock pin (SCK) must be LOW during each CS falling edge. Typically, CS remains LOW during the data output state.
LTC2410 U U W U APPLICATIO S I FOR ATIO 2.7V TO 5.5V VCC 1µF 2 VCC FO = 50Hz REJECTION = EXTERNAL OSCILLATOR = 60Hz REJECTION 14 LTC2410 REFERENCE VOLTAGE 0.1V TO VCC 3 REF + 4 REF – ANALOG INPUT RANGE –0.5VREF TO 0.
LTC2410 U U W U APPLICATIO S I FOR ATIO 2.7V TO 5.5V VCC 1µF 2 VCC FO = 50Hz REJECTION = EXTERNAL OSCILLATOR = 60Hz REJECTION 14 LTC2410 REFERENCE VOLTAGE 0.1V TO VCC 3 REF + 4 REF – ANALOG INPUT RANGE –0.5VREF TO 0.5VREF 5 + SDO IN – CS IN 6 1, 7, 8, 9, 10, 15, 16 SCK 13 2-WIRE INTERFACE 12 11 GND CS BIT 31 SDO BIT 30 EOC BIT 29 BIT 28 SIG MSB BIT 27 BIT 26 BIT 0 BIT 5 LSB24 SCK (EXTERNAL) CONVERSION SLEEP DATA OUTPUT CONVERSION 2410 F07 Figure 7.
LTC2410 U U W U APPLICATIO S I FOR ATIO frequency fEOSC, then tEOCtest is 3.6/fEOSC. If CS is pulled HIGH before time tEOCtest, the device remains in the sleep state. The conversion result is held in the internal static shift register. new conversion. This is useful for systems not requiring all 32 bits of output data, aborting an invalid conversion cycle, or synchronizing the start of a conversion.
LTC2410 U U W U APPLICATIO S I FOR ATIO weak pull-up is active during the POR cycle; therefore, the internal serial clock timing mode is automatically selected if SCK is not externally driven LOW (if SCK is loaded such that the internal pull-up cannot pull the pin HIGH, the external SCK mode will be selected). A similar situation may occur during the sleep state when CS is pulsed HIGH-LOW-HIGH in order to test the conversion status. If the device is in the sleep state (EOC = 0), SCK will go LOW.
LTC2410 U W U U APPLICATIO S I FOR ATIO Internal Serial Clock, Autostart Conversion used to shift the conversion result into external circuitry. After the 32nd rising edge, CS is pulled HIGH and a new conversion is immediately started. This is useful in applications requiring periodic monitoring and ultralow power. Figure 14 shows the average supply current as a function of capacitance on CS.
LTC2410 U W U U APPLICATIO S I FOR ATIO 7 CS is discharging; therefore, the internal serial clock timing mode is automatically selected if SCK is floating. It is important to ensure there are no external drivers pulling SCK LOW while CS is discharging. 6 tSAMPLE (SEC) 5 4 3 PRESERVING THE CONVERTER ACCURACY 2 VCC = 5V 1 VCC = 3V 0 1 10 100 1000 10000 CAPACITANCE ON CS (pF) 100000 2400 F12 Figure 12.
LTC2410 U W U U APPLICATIO S I FOR ATIO velocity is approximately 183ps/inch for internal traces and 170ps/inch for surface traces. Thus, a driver generating a control signal with a minimum transition time of 1ns must be connected to the converter pin through a trace shorter than 2.5 inches. This problem becomes particularly difficult when shared control lines are used and multiple reflections may occur.
LTC2410 U U W U APPLICATIO S I FOR ATIO IREF+ VCC RSW (TYP) 20k ILEAK − VREFCM ( )AVG = VIN + V0INCM .5 • REQ −V + V −V = IN INCM REFCM I(IN− ) AVG 0.5 • REQ I IN+ VREF+ ILEAK VCC IIN+ ILEAK RSW (TYP) 20k VIN+ CEQ 18pF (TYP) ILEAK VCC IIN – RSW (TYP) 20k ILEAK ( + VREFCM IN − )AVG = 1.5 • VREF0−.5V•INCM REQ VREF • REQ ( + VREFCM IN + )AVG = −1.5 • VREF0.
LTC2410 U W U U APPLICATIO S I FOR ATIO For relatively small values of input capacitance (CIN < 0.01µF), the voltage on the sampling capacitor settles almost completely and relatively large values for the source impedance result in only small errors. Such values for CIN will deteriorate the converter offset and gain performance without significant benefits of signal filtering and the user is advised to avoid them.
LTC2410 U U W U APPLICATIO S I FOR ATIO +FS ERROR (ppm OF VREF) 300 VCC = 5V REF + = 5V REF – = GND IN + = 3.75V IN – = 1.25V FO = GND TA = 25°C 240 180 In addition to the input sampling charge, the input ESD protection diodes have a temperature dependent leakage current. This current, nominally 1nA (±10nA max), results in a small offset shift. A 100Ω source resistance will create a 0.1µV typical and 1µV maximum offset voltage. CIN = 1µF, 10µF CIN = 0.1µF 120 Reference Current CIN = 0.
LTC2410 U U W U APPLICATIO S I FOR ATIO REF+ and REF– pins and external capacitance CREF connected to these pins are shown in Figures 22, 23, 24 and␣ 25. In addition to this gain error, the converter INL performance is degraded by the reference source impedance. When FO = LOW (internal oscillator and 60Hz notch), every 100Ω of source resistance driving REF+ or REF– translates into about 1.34ppm additional INL error.
LTC2410 U W U U APPLICATIO S I FOR ATIO 15 RSOURCE = 1000Ω 12 INL (ppm OF VREF) 9 RSOURCE = 500Ω 6 3 0 –3 RSOURCE = 100Ω –6 –9 –12 –15 –0.5 –0.4–0.3–0.2–0.1 0 0.1 0.2 0.3 0.4 0.5 VINDIF/VREFDIF VCC = 5V FO = GND REF+ = 5V CREF = 10µF TA = 25°C REF– = GND 2410 F26 VINCM = 0.5 • (IN + + IN –) = 2.5V Figure 26.
LTC2410 U W U U APPLICATIO S I FOR ATIO 500 VCC = 5V REF + = 5V REF – = GND VINCM = 2.5V VIN = 0V FO = EXTERNAL OSCILLATOR 450 OFFSET ERROR (ppm OF VREF) ity. Typical measured performance curves for output data rates up to 100 readings per second are shown in Figures␣ 27, 28, 29, 30, 31, 32, 33 and 34.
LTC2410 U U W U APPLICATIO S I FOR ATIO 24 22 RESOLUTION = LOG2(VREF/INLMAX) 23 20 TA = 25°C 21 20 TA = 85°C 19 18 VCC = 5V REF + = 5V REF – = GND VINCM = 2.5V VIN = 0V FO = EXTERNAL OSCILLATOR RESOLUTION = LOG2(VREF/NOISERMS) 17 16 15 14 13 12 0 RESOLUTION (BITS) RESOLUTION (BITS) 22 18 TA = 85°C 14 VCC = 5V REF + = 5V REF – = GND VINCM = 2.5V –2.5V < VIN < 2.
LTC2410 U W U U APPLICATIO S I FOR ATIO When external amplifiers are driving the LTC2410, the ADC input referred system noise calculation can be simplified by Figure 36. The noise of an amplifier driving the LTC2410 input pin can be modeled as a band limited white noise source. Its bandwidth can be approximated by the bandwidth of a single pole lowpass filter with a corner frequency fi. The amplifier noise spectral density is ni.
LTC2410 U W U U APPLICATIO S I FOR ATIO The combined normal mode rejection performance is shown in Figure␣ 37 for the internal oscillator with 50Hz notch setting (FO = HIGH) and in Figure␣ 38 for the internal oscillator with 60Hz notch setting (FO = LOW) and for the external oscillator mode. The regions of low rejection occurring at integer multiples of fS have a very narrow bandwidth.
LTC2410 U U W U APPLICATIO S I FOR ATIO Traditional high order delta-sigma modulators, while providing very good linearity and resolution, suffer from potential instabilities at large input signal levels. The proprietary architecture used for the LTC2410 third order modulator resolves this problem and guarantees a predictable stable behavior at input signal levels of up to 150% of full scale.
LTC2410 U W U U APPLICATIO S I FOR ATIO Simultaneous Sampling with Two LTC2410s One such application is synchronizing multiple LTC2410s, see Figure 45. The start of conversion is synchronized to the rising edge of CS. In order to synchronize multiple LTC2410s, CS is a common input to all the ADCs.
LTC2410 U U W U APPLICATIO S I FOR ATIO VREF+ VREF – EXTERNAL OSCILLATOR (153,600HZ) LTC2410 #2 LTC2410 #1 VCC VCC FO VCC LTC2410 #4 FO VCC FO REF + SCK REF + SCK REF + SCK REF + SCK REF – SDO REF – SDO REF – SDO REF – SDO IN + µCONTROLLER FO LTC2410 #3 CS IN + CS IN + CS IN + IN – IN – IN – IN – GND GND GND GND CS SCK SDO CS1 CS2 CS3 CS4 CS1 CS2 CS3 CS4 SCK 31 OR LESS CLOCK PULSES SDO 2410 F46 Figure 46.
LTC2410 U U W U APPLICATIO S I FOR ATIO techniques is used to produce a precision divide operation on the reference signal. Another option is the use of a reference within the 5V input range of the LTC2410 and developing excitation via fixed gain, or LTC1043 based voltage multiplication, along with remote feedback in the excitation amplifiers, as shown in Figures 52 and 53. Figure 47 shows an example of a simple bridge connection.
LTC2410 U U W U APPLICATIO S I FOR ATIO Remote Half Bridge Interface mentation amplifier is used at low gain. If this amplifier is used at a gain of 10, the gain error is only 10ppm and input referred noise is reduced to 0.1µVRMS. The buffer stages can also be configured to provide gain of up to 50 with high gain stability and linearity. As opposed to full bridge applications, typical half bridge applications must contend with nonlinearity in the bridge output, as signal swing is often much greater.
LTC2410 U U W U APPLICATIO S I FOR ATIO reference inputs do not have the same rejection. If 60Hz or other noise is present on the reference input, a low pass filter is recommended as shown in Figure 51. Note that you cannot place a large capacitor directly at the junction of R1 and R2, as it will store charge from the sampling process. A better approach is to produce a low pass filter decoupled from the input lines with a high value resistor (R3).
LTC2410 U W U U APPLICATIO S I FOR ATIO The error associated with the 10V excitation would be –80ppm. Hence, overall reference error could be as high as 130ppm, the average of the two. Figure 54 shows the use of an LTC2410 with a differential multiplexer. This is an inexpensive multiplexer that will contribute some error due to leakage if used directly with the output from the bridge, or if resistors are inserted as a protection mechanism from overvoltage.
LTC2410 U U W U APPLICATIO S I FOR ATIO 15V 7 20Ω Q1 2N3904 6 + – 10V 3 200Ω 2 LT1236-5 10V + 47µF 11 0.1µF * 12 14 13 + 10µF 0.1µF 1k 5V 7 1µF –15V 33Ω 8 + LTC1150 4 350Ω BRIDGE 15V U1 4 LTC1043 15V 17 10V 5V 0.1µF 2 VCC LTC2410 3 –10V REF + 4 REF – 33Ω 5 IN + 6 IN – U2 LTC1043 15V 7 Q2 2N3906 6 + 3 5 LTC1150 20Ω 4 –15V – 1, 7, 8, 9, 10, 15, 16 6 2 2 * 3 –15V 1k GND 15 18 0.
LTC2410 U U W U APPLICATIO S I FOR ATIO 15V + 20Ω Q1 2N3904 1/2 LT1112 1 – C1 0.1µF 22Ω 5V 3 LT1236-5 + C3 47µF 2 C1 0.1µF RN1 10k 10V 1 5V 2 3 4 350Ω BRIDGE TWO ELEMENTS VARYING 2 RN1 10k VCC LTC2410 –5V 8 RN1 10k 5 7 REF + 4 REF – 5 IN + 6 IN – RN1 10k GND 1, 7, 8, 9, 10, 15, 16 6 15V C2 0.1µF 33Ω ×2 Q2, Q3 2N3906 ×2 3 20Ω RN1 IS CADDOCK T914 10K-010-02 8 – 1/2 LT1112 7 + 4 6 5 –15V –15V 2410 F53 Figure 53.
LTC2410 U TYPICAL APPLICATIO S The performance of the LTC2410 can be verified using the demonstration board DC291A, see Figure 57 for the schematic. This circuit uses the computer’s serial port to generate power and the SPI digital signals necessary for starting a conversion and reading the result. It includes a Labview application software program (see Figure 58) which graphically captures the conversion results.
LTC2410 U TYPICAL APPLICATIO S ***************************************************** * This example program transfers the LTC2410's 32-bit output * * conversion result into four consecutive 8-bit memory locations.
LTC2410 U TYPICAL APPLICATIO S ********************************** * The next short loop waits for the * * LTC2410's conversion to finish before * * starting the SPI data transfer * ********************************** * CONVEND LDAA PORTD Retrieve the contents of port D ANDA #%00000100 Look at bit 2 * Bit 2 = Hi; the LTC2410's conversion is not * complete * Bit 2 = Lo; the LTC2410's conversion is complete BNE CONVEND Branch to the loop's beginning while bit 2 remains high * * ******************** * The SPI d
LTC2410 U TYPICAL APPLICATIO S VCC U1 LT1460ACN8-2.5 JP1 JUMPER 1 3 2 6 VOUT VIN GND C1 + 10µF 35V R2 3Ω VCC 2 + U2 LT1236ACN8-5 JP2 JUMPER 1 2 + C2 22µF 25V 4 6 VOUT VIN GND C3 4 10µF 35V 10 1 VCC J5 GND BANANA JACK J6 1 REF + 1 C6 0.
LTC2410 U PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. GN Package 16-Lead Plastic SSOP (Narrow 0.150) (LTC DWG # 05-08-1641) 0.189 – 0.196* (4.801 – 4.978) 0.015 ± 0.004 × 45° (0.38 ± 0.10) 0.007 – 0.0098 (0.178 – 0.249) 0.053 – 0.068 (1.351 – 1.727) 0.004 – 0.0098 (0.102 – 0.249) 16 15 14 13 12 11 10 9 0.009 (0.229) REF 0° – 8° TYP 0.016 – 0.050 (0.406 – 1.270) 0.008 – 0.012 (0.203 – 0.305) * DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.
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