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LTC2414/LTC2418

241418fa

APPLICATIO S

FEATURES

DESCRIPTIO

TYPICAL APPLICATIO

The LTC

2414/LTC2418 are 8-/16-channel (4-/8-differ-

ential) micropower 24-bit ∆Σ analog-to-digital convert-

ers. They operate from 2.7V to 5.5V and include an

integrated oscillator, 2ppm INL and 0.2ppm RMS noise.

They use delta-sigma technology and provide single cycle

settling time for multiplexed applications. Through a

single pin, the

LTC2414/LTC2418

can be configured for

better than 110dB differential mode rejection at 50Hz or

60Hz ±2%, or they can be driven by an external oscillator

for a user-defined rejection frequency. The internal oscil-

lator requires no external frequency setting components.

The LTC2414/LTC2418 accept any external differential

reference voltage from 0.1V to V

for flexible ratiometric

and remote sensing measurement applications. They can

be configured to take 4/8 differential channels or

8/16 single-ended channels. The full-scale bipolar input

range is from – 0.5V

REF

to 0.5V

REF

. The reference common

mode voltage, V

REFCM

, and the input common mode volt-

age, V

INCM

, may be independently set within GND to V

The DC common mode input rejection is better than 140dB.

The LTC2414/LTC2418 communicate through a flexible

4-wire digital interface that is compatible with SPI and

MICROWIRE

protocols.

■

Direct Sensor Digitizer

■

Weight Scales

■

Direct Temperature Measurement

■

Gas Analyzers

■

Strain Gauge Transducers

■

Instrumentation

■

Data Acquisition

■

Industrial Process Control

, LTC and LT are registered trademarks of Linear Technology Corporation.

■

8-/16-Channel Single-Ended or 4-/8-Channel

Differential Inputs (LTC2414/LTC2418)

■

Low Supply Current (200µA, 4µA in Autosleep)

■

Differential Input and Differential Reference

with GND to V

Common Mode Range

■

2ppm INL, No Missing Codes

■

2.5ppm Full-Scale Error and 0.5ppm Offset

■

0.2ppm Noise

■

No Latency: Digital Filter Settles in a Single Cycle

Each Conversion Is Accurate, Even After a New

Channel is Selected

■

Single Supply 2.7V to 5.5V Operation

■

Internal Oscillator—No External Components

Required

■

110dB Min, 50Hz/60Hz Notch Filter

8-/16-Channel

24-Bit No Latency ∆Σ

ADCs

No Latency ∆Σ is a trademark of Linear Technology Corporation. All other trademarks are the

property of their respective owners.

Total Unadjusted Error

vs Input Voltage

SDI

SCK

SDO

REF

911

2.7V TO 5.5V

1µF

COM

REF

–

GND

THERMOCOUPLE

DIFFERENTIAL

24-BIT ∆Σ ADC

16-CHANNEL

MUX

–

241418 TA01a

4-WIRE

SPI INTERFACE

LTC2418

= 50Hz REJECTION

= EXTERNAL OSCILLATOR

= 60Hz REJECTION

CH0

CH1

•

CH7

CH8

CH15

INPUT VOLTAGE (V)

–2.5 –2 –1 0 1.0 2.0

TUE (ppm OF V

REF

)

–1

–2

–3

–1.5 –0.5 0.5 1.5

2414/18 TA01b

2.5

= 5V

REF

= 5V

INCM

= V

REFCM

= 2.5V

= GND

= 85°C

= 25°C

= –45°C

Summary of content (48 pages)

PAGE 1
LTC2414/LTC2418 8-/16-Channel 24-Bit No Latency ∆ΣTM ADCs U FEATURES DESCRIPTIO ■ The LTC®2414/LTC2418 are 8-/16-channel (4-/8-differential) micropower 24-bit ∆Σ analog-to-digital converters. They operate from 2.7V to 5.5V and include an integrated oscillator, 2ppm INL and 0.2ppm RMS noise. They use delta-sigma technology and provide single cycle settling time for multiplexed applications.
PAGE 2
LTC2414/LTC2418 W W W AXI U U ABSOLUTE RATI GS (Notes 1, 2) Supply Voltage (VCC) to GND .......................– 0.3V to 7V Analog Input Voltage to GND ....... – 0.3V to (VCC + 0.3V) Reference Input Voltage to GND .. – 0.3V to (VCC + 0.3V) Digital Input Voltage to GND ........ – 0.3V to (VCC + 0.3V) Digital Output Voltage to GND ..... – 0.3V to (VCC + 0.3V) Operating Temperature Range LTC2414/LTC2418C ................................ 0°C to 70°C LTC2414/LTC2418I ............................
PAGE 3
LTC2414/LTC2418 ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4) PARAMETER CONDITIONS MIN Resolution (No Missing Codes) 0.1V ≤ VREF ≤ VCC, – 0.5 • VREF ≤ VIN ≤ 0.5 • VREF (Note 5) Integral Nonlinearity 4.5V ≤ VCC ≤ 5.5V, REF + = 2.5V, REF– = GND, VINCM = 1.25V (Note 6) 5V ≤ VCC ≤ 5.5V, REF + = 5V, REF – = GND, VINCM = 2.5V (Note 6) REF + = 2.5V, REF – = GND, VINCM = 1.
PAGE 4
LTC2414/LTC2418 U U U U A ALOG I PUT A D REFERE CE The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) SYMBOL PARAMETER IN + Absolute/Common Mode IN + Voltage CONDITIONS ● GND – 0.3 MIN TYP VCC + 0.3 MAX UNITS V IN – Absolute/Common Mode IN – Voltage ● GND – 0.3 VCC + 0.3 V VIN Input Differential Voltage Range (IN + – IN –) ● – VREF/2 VREF/2 V REF + Absolute/Common Mode REF + Voltage ● 0.
PAGE 5
LTC2414/LTC2418 U U DIGITAL I PUTS A D DIGITAL OUTPUTS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) SYMBOL PARAMETER CONDITIONS VOL Low Level Output Voltage SDO IO = 1.6mA ● MIN VOH High Level Output Voltage SCK IO = – 800µA (Note 10) ● VOL Low Level Output Voltage SCK IO = 1.6mA (Note 10) ● IOZ Hi-Z Output Leakage SDO ● TYP MAX UNITS 0.4 V VCC – 0.5 V –10 0.
PAGE 6
LTC2414/LTC2418 WU TI I G CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
PAGE 7
LTC2414/LTC2418 U W TYPICAL PERFOR A CE CHARACTERISTICS Total Unadjusted Error (VCC = 5V, VREF = 5V) FO = GND TA = –45°C 6 VCC = 2.7V VREF = 2.5V = VREFCM = 1.25V V 4 INCM 0 TA = –45°C –1 TA = 85°C TUE (ppm OF VREF) TA = 25°C 1 TA = 25°C 0 TA = 85°C –1 TA = –45°C –2 –2 –3 –2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 INPUT VOLTAGE (V) –3 –1.25 –0.75 –8 –1.25 1.25 –0.25 0.25 0.75 INPUT VOLTAGE (V) 8 FO = GND 6 VCC = 2.7V VREF = 2.5V = VREFCM = 1.
PAGE 8
LTC2414/LTC2418 U W TYPICAL PERFOR A CE CHARACTERISTICS RMS Noise vs Input Differential Voltage 1.0 FO = GND TA = 25°C VCC = 5V 0.4 V REF = 5V VINCM = 2.5V RMS Noise vs Temperature (TA) RMS Noise vs VINCM 1.2 1.1 0.9 0.3 0.2 0.8 FO = GND TA = 25°C VCC = 5V REF+ = 5V REF – = GND VIN = 0V VINCM = GND 0.7 0.6 0.1 0.5 0 –2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 INPUT DIFFERENTIAL VOLTAGE (V) –1 1 0 3 2 VINCM (V) 4 5 0.9 0.8 FO = GND VCC = 5V VREF = 5V VIN = 0V VINCM = GND 0.7 0.6 0.
PAGE 9
LTC2414/LTC2418 U W TYPICAL PERFOR A CE CHARACTERISTICS Full-Scale Error vs Temperature +FS ERROR 1 0 –1 –2 –FS ERROR –3 –4 –5 –60 –40 –20 0 20 40 60 TEMPERATURE (°C) 80 Full-Scale Error vs VREF Full-Scale Error vs VCC 5 5 4 3 FULL-SCALE ERROR (ppm OF VREF) FO = GND 4 VCC = 5V = 5V V 3 REF VINCM = 2.5V 2 FULL-SCALE ERROR (ppm OF VREF) FULL-SCALE ERROR (ppm OF VREF) 5 +FS ERROR 2 FO = GND 1 T = 25°C A 0 VREF = 2.5V VINCM = 0.5VREF –1 REF – = GND –FS ERROR –2 –3 –4 –5 100 2.7 3.1 3.
PAGE 10
LTC2414/LTC2418 U U U PI FU CTIO S CH0 to CH15 (Pin 21 to Pin 28 and Pin 1 to Pin 8): Analog Inputs. May be programmed for single-ended or differential mode. CH8 to CH15 (Pin 1 to Pin 8) not connected on the LTC2414. is in a high impedance state. During the Conversion and Sleep periods, this pin is used as the conversion status output. The conversion status can be observed by pulling CS LOW. VCC (Pin 9): Positive Supply Voltage. Bypass to GND (Pin 15) with a 10µF tantalum capacitor in parallel with 0.
PAGE 11
LTC2414/LTC2418 W FU CTIO AL BLOCK DIAGRA U INTERNAL OSCILLATOR U VCC GND REF REF – CH0 CH1 CH15 COM FO (INT/EXT) AUTOCALIBRATION AND CONTROL + – IN + • • • MUX IN – + DIFFERENTIAL 3RD ORDER ∆Σ MODULATOR SDI SCK SDO CS SERIAL INTERFACE DECIMATING FIR ADDRESS 241418 F01 Figure 1 TEST CIRCUITS VCC 1.69k SDO SDO 1.
PAGE 12
LTC2414/LTC2418 U W U U APPLICATIO S I FOR ATIO POWER UP IN + = CH0, IN – = CH1 CONVERT SLEEP FALSE CS = LOW AND SCK TRUE DATA OUTPUT ADDRESS INPUT 241418 F02 Figure 2. LTC2414/LTC2418 State Transition Diagram first rising edge of SCK and depending on the control bits, the converter updates its channel selection immediately and is valid for the next conversion. The details of channel selection control bits are described in the Input Data Mode section.
PAGE 13
LTC2414/LTC2418 U W U U APPLICATIO S I FOR ATIO specification for the REF + and REF – pins covers the entire range from GND to VCC. For correct converter operation, the REF + pin must always be more positive than the REF – pin. The LTC2414/LTC2418 can accept a differential reference voltage from 0.1V to VCC. The converter output noise is determined by the thermal noise of the front-end circuits, and, as such, its value in nanovolts is nearly constant with reference voltage.
PAGE 14
LTC2414/LTC2418 U W U U APPLICATIO S I FOR ATIO CS SDO Hi-Z BIT31 BIT30 BIT29 BIT28 BIT27 EOC DMY SIG MSB B22 BIT26 BIT25 BIT24 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 LSB SGL ODD/ SIGN A2 A1 A0 PARITY ADDRESS CORRESPONDING TO RESULT CONVERSON RESULT SCK SDI 1 0 EN SGL ODD/ SIGN A2 A1 A0 SLEEP DON’T CARE CONVERSION DATA INPUT/OUTPUT 241418 F03a Figure 3a.
PAGE 15
LTC2414/LTC2418 U W U U APPLICATIO S I FOR ATIO Table 2.
PAGE 16
LTC2414/LTC2418 U W U U APPLICATIO S I FOR ATIO parity bit representing the parity of the previous 31 bits. The parity bit is useful to check the output data integrity especially when the output data is transmitted over a distance. The third and fourth bits together are also used to indicate an underrange condition (the differential input voltage is below – FS) or an overrange condition (the differential input voltage is above + FS). Bit 31 (first output bit) is the end of conversion (EOC) indicator.
PAGE 17
LTC2414/LTC2418 U W U U APPLICATIO S I FOR ATIO Table 4. LTC2414/LTC2418 Output Data Format Differential Input Voltage VIN * Bit 31 EOC Bit 30 DMY Bit 29 SIG Bit 28 MSB Bit 27 Bit 26 Bit 25 … Bit 6 LSB VIN* ≥ 0.5 • VREF** 0 0 1 1 0 0 0 … 0 0.5 • VREF** – 1LSB 0 0 1 0 1 1 1 … 1 0.25 • VREF** 0 0 1 0 1 0 0 … 0 0.25 • VREF** – 1LSB 0 0 1 0 0 1 1 … 1 0 0 0 1 0 0 0 0 … 0 –1LSB 0 0 0 1 1 1 1 … 1 – 0.
PAGE 18
LTC2414/LTC2418 U W U U APPLICATIO S I FOR ATIO Table 5. LTC2414/LTC2418 State Duration State Operating Mode CONVERT Internal Oscillator External Oscillator Duration FO = LOW (60Hz Rejection) 133ms, Output Data Rate ≤ 7.5 Readings/s FO = HIGH (50Hz Rejection) 160ms, Output Data Rate ≤ 6.
PAGE 19
LTC2414/LTC2418 U W U U APPLICATIO S I FOR ATIO last input bit A0 of SDI by the time CS pulled HIGH, the address information is discarded and the previous address is kept. nal serial clock, 3- or 4-wire I/O, single cycle conversion. The following sections describe each of these serial interface timing modes in detail. In all these cases, the converter can use the internal oscillator (FO = LOW or FO = HIGH) or an external oscillator connected to the FO pin. Refer to Table 6 for a summary.
PAGE 20
LTC2414/LTC2418 U W U U APPLICATIO S I FOR ATIO and the last bit of the conversion result can be latched on the 32nd rising edge of SCK. On the 32nd falling edge of SCK, the device begins a new conversion. SDO goes HIGH (EOC = 1) indicating a conversion is in progress. The serial clock mode is selected on the falling edge of CS. To select the external serial clock mode, the serial clock pin (SCK) must be LOW during each CS falling edge. The serial data output pin (SDO) is Hi-Z as long as CS is HIGH.
PAGE 21
LTC2414/LTC2418 U W U U APPLICATIO S I FOR ATIO External Serial Clock, 3-Wire I/O each falling edge of SCK. EOC can be latched on the first rising edge of SCK. On the 32nd falling edge of SCK, SDO goes HIGH (EOC = 1) indicating a new conversion has begun. This timing mode utilizes a 3-wire serial I/O interface. The conversion result is shifted out of the device by an externally generated serial clock (SCK) signal, see Figure 7.
PAGE 22
LTC2414/LTC2418 U W U U APPLICATIO S I FOR ATIO 2.7V TO 5.5V VCC 1µF 9 VCC FO = 50Hz REJECTION = EXTERNAL OSCILLATOR = 60Hz REJECTION 19 LTC2414/ LTC2418 REFERENCE VOLTAGE 0.
PAGE 23
LTC2414/LTC2418 U W U U APPLICATIO S I FOR ATIO 2.7V TO 5.5V VCC 1µF 9 VCC FO = 50Hz REJECTION = EXTERNAL OSCILLATOR = 60Hz REJECTION 19 LTC2414/ LTC2418 REFERENCE VOLTAGE 0.
PAGE 24
LTC2414/LTC2418 U W U U APPLICATIO S I FOR ATIO 2.7V TO 5.5V VCC 1µF 9 VCC FO = 50Hz REJECTION = EXTERNAL OSCILLATOR = 60Hz REJECTION 19 LTC2414/ LTC2418 REFERENCE VOLTAGE 0.
PAGE 25
LTC2414/LTC2418 U W U U APPLICATIO S I FOR ATIO operation, it is recommended to drive all digital input signals to full CMOS levels [V IL < 0.4V and VOH > (VCC – 0.4V)]. During the conversion period, the undershoot and/or overshoot of a fast digital signal connected to the pins may severely disturb the analog to digital conversion process.
PAGE 26
LTC2414/LTC2418 U W U U APPLICATIO S I FOR ATIO Input Current If complete settling occurs on the input, conversion results will be unaffected by the dynamic input current. An incomplete settling of the input signal sampling process may result in gain and offset errors, but it will not degrade the INL performance of the converter.
PAGE 27
LTC2414/LTC2418 U W U U APPLICATIO S I FOR ATIO RSOURCE VINCM + 0.5VIN IN + CIN CPAR ≅ 20pF RSOURCE VINCM – 0.5VIN LTC2414/ LTC2418 IN – CIN CPAR ≅ 20pF 2414/18 F12 Figure 12. An RC Network at IN+ and IN– 50 0 CIN = 0.01µF VCC = 5V REF + = 5V REF – = GND IN + = 1.25V IN – = 3.75V FO = GND TA = 25°C 40 –FS ERROR (ppm OF VREF) +FS ERROR (ppm OF VREF) CIN = 0.001µF CIN = 100pF CIN = 0pF 30 VCC = 5V REF + = 5V REF – = GND IN + = 3.75V IN – = 1.
PAGE 28
LTC2414/LTC2418 U W U U APPLICATIO S I FOR ATIO 1.78 • 10–6 • fEOSCppm. Figure 17 shows the typical offset error due to input common mode voltage for various values of source resistance imbalance between the IN+ and IN– pins when large CIN values are used. +FS ERROR (ppm OF VREF) 300 VCC = 5V REF + = 5V REF – = GND IN + = 3.75V IN – = 1.25V FO = GND TA = 25°C 240 180 CIN = 1µF, 10µF CIN = 0.1µF 120 CIN = 0.01µF 60 0 0 100 200 300 400 500 600 700 800 900 1000 RSOURCE (Ω) 2414/18 F15 Figure 15.
PAGE 29
LTC2414/LTC2418 U W U U APPLICATIO S I FOR ATIO values for CREF will deteriorate the converter offset and gain performance without significant benefits of reference filtering and the user is advised to avoid them. Larger values of reference capacitors (CREF > 0.01µF) may be required as reference filters in certain configurations. Such capacitors will average the reference sampling charge and the external source resistance will see a quasi constant reference differential impedance.
PAGE 30
LTC2414/LTC2418 U W U U APPLICATIO S I FOR ATIO In addition to this gain error, the converter INL performance is degraded by the reference source impedance. When FO = LOW (internal oscillator and 60Hz notch), every 100Ω of source resistance driving REF+ or REF– translates into about 1.34ppm additional INL error. When FO = HIGH (internal oscillator and 50Hz notch), every 100Ω of source resistance driving REF+ or REF– translates into about 1.1ppm additional INL error.
PAGE 31
LTC2414/LTC2418 U W U U APPLICATIO S I FOR ATIO Third, an increase in the frequency of the external oscillator above 460800Hz (a more than 3× increase in the output data rate) will start to decrease the effectiveness of the internal autocalibration circuits. This will result in a progressive degradation in the converter accuracy and linearity. Typical measured performance curves for output data rates up to 100 readings per second are shown in Figures 23, 24, 25, 26, 27, 28, 29 and 30.
PAGE 32
LTC2414/LTC2418 U W U U APPLICATIO S I FOR ATIO 22 24 23 20 RESOLUTION (BITS) TA = 85°C 19 18 VCC = 5V REF + = 5V REF – = GND VINCM = 2.5V VIN = 0V SDI = GND FO = EXTERNAL OSCILLATOR RESOLUTION = LOG2(VREF/NOISERMS) 17 16 15 14 13 0 18 TA = 85°C TA = 25°C 16 14 VCC = 5V REF + = 5V REF – = GND VINCM = 2.5V –2.5V < VIN < 2.5V SDI = GND FO = EXTERNAL OSCILLATOR 12 10 8 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 0 VREF = 5V VREF = 2.
PAGE 33
LTC2414/LTC2418 U W U U APPLICATIO S I FOR ATIO INPUT REFERRED NOISE EQUIVALENT BANDWIDTH (Hz) 100 FO = LOW 10 FO = HIGH 1 0.1 0.1 1 10 100 1k 10k 100k 1M INPUT NOISE SOURCE SINGLE POLE EQUIVALENT BANDWIDTH (Hz) 2414/18 F32 Figure 32. Input Referred Noise Equivalent Bandwidth of an Input Connected White Noise Source 0 INPUT NORMAL MODE REJECTION (dB) When external amplifiers are driving the LTC2414/ LTC2418, the ADC input referred system noise calculation can be simplified by Figure 32.
PAGE 34
LTC2414/LTC2418 U W U U APPLICATIO S I FOR ATIO The combined normal mode rejection performance is shown in Figure 33 for the internal oscillator with 50Hz notch setting (FO = HIGH) and in Figure 34 for the internal oscillator with 60Hz notch setting (FO = LOW) and for the external oscillator mode. The regions of low rejection occurring at integer multiples of fS have a very narrow bandwidth.
PAGE 35
LTC2414/LTC2418 U W U U APPLICATIO S I FOR ATIO Traditional high order delta-sigma modulators, while providing very good linearity and resolution, suffer from potential instabilities at large input signal levels. The proprietary architecture used for the LTC2414/LTC2418 third order modulator resolves this problem and guarantees a predictable stable behavior at input signal levels of up to 150% of full scale.
PAGE 36
LTC2414/LTC2418 U W U U APPLICATIO S I FOR ATIO BRIDGE APPLICATIONS Typical strain gauge based bridges deliver only 2mV/Volt of excitation. As the maximum reference voltage of the LTC2414/LTC2418 is 5V, remote sensing of applied excitation without additional circuitry requires that excitation be limited to 5V. This gives only 10mV full scale input signal, which can be resolved to 1 part in 10000 without averaging. For many solid state sensors, this is still better than the sensor.
PAGE 37
LTC2414/LTC2418 U W U U APPLICATIO S I FOR ATIO changes the rationale. Achieving high gain accuracy and linearity at higher gains may prove difficult, while providing little benefit in terms of noise reduction. The circuit in Figure 42 shows an example of a simple amplification scheme. This example produces a differential output with a common mode voltage of 2.5V, as determined by the bridge.
PAGE 38
LTC2414/LTC2418 U W U U APPLICATIO S I FOR ATIO Remote Half Bridge Interface Figure 43 shows an example of a single amplifier used to produce single-ended gain. This topology is best used in applications where the gain setting resistor can be made to match the temperature coefficient of the strain gauges.
PAGE 39
LTC2414/LTC2418 U W U U APPLICATIO S I FOR ATIO The basic circuit shown in Figure 44 shows connections for a full 4-wire connection to the sensor, which may be located remotely. The differential input connections will reject induced or coupled 60Hz interference, however, the reference inputs do not have the same rejection. If 60Hz or other noise is present on the reference input, a low pass filter is recommended as shown in Figure 45.
PAGE 40
LTC2414/LTC2418 U W U U APPLICATIO S I FOR ATIO The error associated with the 10V excitation would be –80ppm. Hence, overall reference error could be as high as 130ppm, the average of the two. is configured to provide 10V and –5V excitation to the bridge, producing a common mode voltage at the input to the LTC2414/LTC2418 of 2.5V, maximizing the AC input range for applications where induced 60Hz could reach amplitudes up to 2VRMS.
PAGE 41
LTC2414/LTC2418 U W U U APPLICATIO S I FOR ATIO 15V + 20Ω Q1 2N3904 1/2 LT1112 1 – C1 0.1µF 22Ω 5V 3 LT1236-5 + C3 47µF 2 C1 0.1µF RN1 10k 10V 1 5V 2 3 4 350Ω BRIDGE TWO ELEMENTS VARYING 9 RN1 10k VCC LTC2414/ LTC2418 11 REF + 12 REF – 21 –5V 22 8 RN1 10k 5 7 CH1 GND 15 6 15V C2 0.1µF 33Ω ×2 Q2, Q3 2N3906 ×2 RN1 10k CH0 20Ω 7 RN1 IS CADDOCK T914 10K-010-02 8 – 1/2 LT1112 4 –15V –15V + 6 5 2410 F53 Figure 47.
PAGE 42
LTC2414/LTC2418 U W U U APPLICATIO S I FOR ATIO Figure 49 shows the 4-wire SPI connection between the LTC2414/LTC2418 and a PIC16F84 microcontroller. The sample program for CC5X compiler in Figure 50 can be used to program the PIC16F84 to control the LTC2414/ LTC2418. It uses PORT B to interface with the device. 5V 0.1µF + 10µF R1 25k 0.
PAGE 43
LTC2414/LTC2418 U W U U APPLICATIO S I FOR ATIO // LTC2418 PIC16F84 Interface Example // Written for CC5X Compiler // Processor is PIC16F84 running at 10 MHz #include <16f84.h> #include #pragma origin = 0x4 #pragma config |= 0x3fff, WDTE=off,FOSC=HS // global pin definitions: #pragma bit rx_pin #pragma bit tx_pin #pragma bit sck #pragma bit sdi #pragma bit sdo #pragma bit cs_bar @ @ @ @ @ @ PORTB.0 PORTB.1 PORTB.2 PORTB.3 PORTB.4 PORTB.
PAGE 44
LTC2414/LTC2418 U W U U APPLICATIO S I FOR ATIO ////////// Bidirectional Shift Routine for ADC ////////// void shiftbidir(char nextch) { int i; for(i=0;i<2;i++) // send config bits 7:6, // ignore EOC/ and DMY bits { sdi=nextch.7; nextch = rl(nextch); sck=1; sck=0; // // // // put data on pin get next config bit ready clock high clock low } for(i=0;i<8;i++) // send config, read byte 3 { sdi=nextch.
PAGE 45
LTC2414/LTC2418 U W U U APPLICATIO S I FOR ATIO VCC 1 JP1 JMPR VCC 2.5V 3 C1 + 10µF 35V 2 BANANA JACK J1 VEX J2 REF + J3 REF – J4 1 GND 2.5V JP3 JMPR VIN VOUT GND 2 C3 10µF 35V 3 + VOUT VIN GND E1 R1 10Ω + VEXT E2 C4 100µF 16V GND JP2 JMPR P1 DB9 1 6 2 7 3 8 4 9 5 3 2 NC VCC NC D1 BAV74LT1 U2 LT1236ACN8-5 1 5V 1 JP5 JMPR VCC C2 22µF 25V R2 3Ω VCC E3 1 C6 0.1µF 3 + GND VCC 2 REMOVE TO DISCONNECT VCC AND 5V REF U1 LT1460ACN8-2.
PAGE 46
LTC2414/LTC2418 U W U U APPLICATIO S I FOR ATIO Figure 52. LTC2418 Demo Program Display Top Silkscreen Top Layer Bottom Layer Figure 53.
PAGE 47
LTC2414/LTC2418 U PACKAGE DESCRIPTIO GN Package 28-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) 0.386 – 0.393* (9.804 – 9.982) 28 27 26 25 24 23 22 21 20 19 18 17 1615 0.229 – 0.244 (5.817 – 6.198) 0.150 – 0.157** (3.810 – 3.988) 1 0.015 ± 0.004 × 45° (0.38 ± 0.10) 0.0075 – 0.0098 (0.191 – 0.249) 0.033 (0.838) REF 2 3 4 5 6 7 8 9 10 11 12 13 14 0.053 – 0.069 (1.351 – 1.748) 0.004 – 0.009 (0.102 – 0.249) 0° – 8° TYP 0.016 – 0.050 (0.406 – 1.270) 0.008 – 0.012 (0.
PAGE 48
LTC2414/LTC2418 U TYPICAL APPLICATIO 5V 0.1µF + 10µF 9 11 REF + VCC 12 REF – LTC2418 LTC2418 • • • THERMISTOR 21 CH0 THERMOCOUPLE 22 23 CH1 SDI CH2 SCK 24 CH3 ••• • 7 CH14 8 10 SDO CS CH15 FO 20 18 17 16 19 COM GND 15 2418 F54 Figure 54. Multichannel Bridge Digitizer and Digital Cold Junction Compensation RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1019 Precision Bandgap Reference, 2.5V, 5V 3ppm/°C Drift, 0.