Datasheet

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LTC2421/LTC2422

24212f

1-/2-Channel 20-Bit µPower

No Latency ∆Σ

ADCs in MSOP-10

■

Weight Scales

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Direct Temperature Measurement

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Gas Analyzers

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Strain Gauge Transducers

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Instrumentation

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Data Acquisition

■

Industrial Process Control

No Latency ∆Σ is a trademark of Linear Technology Corporation.

MICROWIRE is a trademark of National Semiconductor Corporation.

Pseudo Differential Bridge Digitizer

, LTC and LT are registered trademarks of Linear Technology Corporation.

The LTC

2421/LTC2422 are 1- and 2-channel 2.7V to 5.5V

micropower 20-bit analog-to-digital converters with an

integrated oscillator, 8ppm INL and 1.2ppm RMS noise.

These ultrasmall devices use delta-sigma technology and

a new digital filter architecture that settles in a single cycle.

This eliminates the latency found in conventional ∆Σ

converters and simplifies multiplexed applications.

Through a single pin, the LTC2421/LTC2422 can be

configured for better than 110dB rejection at 50Hz or

60Hz ±2%, or can be driven by an external oscillator for

a user defined rejection frequency in the range 1Hz to

120Hz. The internal oscillator requires no external fre-

quency setting components.

These converters accept an external reference voltage

from 0.1V to V

. With an extended input conversion

range of –12.5% V

REF

to 112.5% V

REF

= FS

SET

–

SET

), the LTC2421/LTC2422 smoothly resolve the off-

set and overrange problems of preceding sensors or

signal conditioning circuits.

The LTC2421/LTC2422 communicate through a 2- or

3-wire digital interface that is compatible with SPI and

MICROWIRE

protocols.

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20-Bit ADCs in Tiny MSOP-10 Packages

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1- or 2-Channel Inputs

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Single Supply 2.7V to 5.5V Operation

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Low Supply Current (200µA) and Auto Shutdown

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Automatic Channel Selection (Ping-Pong) (LTC2422)

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No Latency: Digital Filter Settles in a

Single Conversion Cycle

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8ppm INL, No Missing Codes

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4ppm Full-Scale Error

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0.5ppm Offset

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1.2ppm Noise

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Zero Scale and Full Scale Set for Reference

and Ground Sensing

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Internal Oscillator—No External Components Required

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110dB Min, 50Hz/60Hz Notch Filter

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Reference Input Voltage: 0.1V to V

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Live Zero—Extended Input Range Accommodates

12.5% Overrange and Underrange

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Pin Compatible with LTC2401/LTC2402

ANALOG INPUT RANGE

SET

– 0.12V

REF

SET

+ 0.12V

REF

= FS

SET

– ZS

SET

)

SET

SCK

CH1 SDO

GND

REFERENCE VOLTAGE

SET

+ 0.1V TO V

0V TO FS

SET

– 100mV

CH0

= INTERNAL OSC/50Hz REJECTION

= EXTERNAL CLOCK SOURCE

= INTERNAL OSC/60Hz REJECTION

3-WIRE

SPI INTERFACE

1µF

110

2.7V TO 5.5V

LTC2422

24212 TA01

SET

SCK

CH0

SDO

CH1

GND

LTC2422

3-WIRE

SPI INTERFACE

INTERNAL OSCILLATOR

60Hz REJECTION

2.7V TO 5.5V

24012TA02

DESCRIPTIO

FEATURES

APPLICATIO S

TYPICAL APPLICATIO

Summary of content (32 pages)

PAGE 1
LTC2421/LTC2422 1-/2-Channel 20-Bit µPower No Latency ∆ΣTMADCs in MSOP-10 U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO 20-Bit ADCs in Tiny MSOP-10 Packages 1- or 2-Channel Inputs Single Supply 2.7V to 5.5V Operation Low Supply Current (200µA) and Auto Shutdown Automatic Channel Selection (Ping-Pong) (LTC2422) No Latency: Digital Filter Settles in a Single Conversion Cycle 8ppm INL, No Missing Codes 4ppm Full-Scale Error 0.5ppm Offset 1.
PAGE 2
LTC2421/LTC2422 W W U W ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) Supply Voltage (VCC) to GND .......................– 0.3V to 7V Analog Input Voltage to GND ....... – 0.3V to (VCC + 0.3V) Reference Input Voltage to GND .. – 0.3V to (VCC + 0.3V) Digital Input Voltage to GND ........ – 0.3V to (VCC + 0.3V) Digital Output Voltage to GND ..... – 0.3V to (VCC + 0.3V) Operating Temperature Range LTC2421/LTC2422C ................................ 0°C to 70°C LTC2421/LTC2422I ............................
PAGE 3
LTC2421/LTC2422 U U U U A ALOG I PUT A D REFERE CE The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VREF = FSSET – ZSSET. (Note 3) SYMBOL PARAMETER CONDITIONS MIN VIN Input Voltage Range (Note 14) FSSET ZSSET CS(IN) Input Sampling Capacitance CS(REF) Reference Sampling Capacitance IIN(LEAK) Input Leakage Current CS = VCC ● –100 1 100 nA IREF(LEAK) Reference Leakage Current VREF = 2.
PAGE 4
LTC2421/LTC2422 WU TI I G CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) SYMBOL PARAMETER CONDITIONS MIN MAX UNITS fEOSC External Oscillator Frequency Range ● 2.56 307.2 kHz tHEO External Oscillator High Period tLEO External Oscillator Low Period ● 0.5 390 µs ● 0.
PAGE 5
LTC2421/LTC2422 U W TYPICAL PERFOR A CE CHARACTERISTICS Total Unadjusted Error (3V Supply) 10 10 VCC = 3V VREF = 2.5V 8 6 4 4 4 2 –2 –4 2 0 –2 0.5 0 1.5 2.0 1.0 INPUT VOLTAGE (V) TA = –55°C, –45°C, 25°C, 90°C –6 –8 2.5 –8 –10 0.5 0 1.5 2.0 1.0 INPUT VOLTAGE (V) 0 2.5 INL (5V Supply) 10 6 4 4 ERROR (ppm) 6 4 2 0 –2 –4 TA = –55°C, –45°C, 25°C, 90°C –6 –8 2.60 2.65 2.70 INPUT VOLTAGE (V) 2.75 –10 2.
PAGE 6
LTC2421/LTC2422 U W TYPICAL PERFOR A CE CHARACTERISTICS RMS Noise vs Reference Voltage 60 Offset Error vs VCC 10 VCC = 5V TA = 25°C VREF = 2.5V TA = 25°C 30 20 5 VREF = 2.5V TA = 25°C 7.5 RMS NOISE (ppm) OFFSET ERROR (ppm) RMS NOISE (ppm OF VREF) 50 40 RMS Noise vs VCC 10.0 0 –5 5.0 2.5 10 0 0 1 –10 5 2 3 4 REFERENCE VOLTAGE (V) 0 2.7 3.2 3.7 4.2 VCC (V) 5.2 5.5 4.7 24212 G10 RMS Noise vs Code Out 5.00 VCC = 5 =5 V 300 VREF= 0 IN 3.75 RMS NOISE (ppm) 200 150 100 3.7 4.
PAGE 7
LTC2421/LTC2422 U W TYPICAL PERFOR A CE CHARACTERISTICS Conversion Current vs Temperature Sleep Current vs Temperature 220 VCC = 4.1V VIN = 0V –20 TA = 25°C FO = 0 VCC = 5.5V 200 VCC = 4.1V 190 180 VCC = 2.7V 170 VCC = 2.
PAGE 8
LTC2421/LTC2422 U W TYPICAL PERFOR A CE CHARACTERISTICS VCC = 5V VREF = 5V FO = EXTERNAL 16 TA = –45°C TA = 25°C 14 TA = 90°C 16 TA = –45°C 14 TA = 25°C TA = 90°C 12 12 10 Resolution vs Output Rate 24 VCC = 3V VREF = 2.
PAGE 9
LTC2421/LTC2422 U U U PIN FUNCTIONS SCK (Pin 9): Bidirectional Digital Clock Pin. In the Internal Serial Clock Operation mode, SCK is used as digital output for the internal serial interface clock during the data output period. In the External Serial Clock Operation mode, SCK is used as digital input for the external serial interface. An internal pull-up current source is automatically activated in Internal Serial Clock Operation mode.
PAGE 10
LTC2421/LTC2422 U W U U APPLICATIO S I FOR ATIO The LTC2421/LTC2422 are pin compatible with the LTC2401/LTC2402. The devices are designed to allow the user to incorporate either device in the same design with no modifications. While the LTC2421/LTC2422 output word length is 24 bits (as opposed to the 32-bit output of the LTC2401/LTC2402), its output clock timing can be identical to the LTC2401/LTC2402.
PAGE 11
LTC2421/LTC2422 U W U U APPLICATIO S I FOR ATIO Conversion Clock above. The first conversion result following POR is accurate within the specifications of the device. A major advantage delta-sigma converters offer over conventional type converters is an on-chip digital filter (commonly known as Sinc or Comb filter). For high resolution, low frequency applications, this filter is typically designed to reject line frequencies of 50Hz or 60Hz plus their harmonics.
PAGE 12
LTC2421/LTC2422 U W U U APPLICATIO S I FOR ATIO fault current, a resistor of up to 5k may be added in series with the VIN pin without affecting the performance of the device. In the physical layout, it is important to maintain the parasitic capacitance of the connection between this series resistance and the VIN pin as low as possible; therefore, the resistor should be located as close as practical to the VIN pin.
PAGE 13
LTC2421/LTC2422 U W U U APPLICATIO S I FOR ATIO Table 2. LTC2421/LTC2422 Output Data Format Bit 23 EOC Bit 22* CH0/CH1 Bit 21 SIG Bit 20 EXR Bit 19 MSB Bit 18 Bit 17 Bit 16 Bit 15 … Bit 0 LSB VIN > 9/8 • VREF 0 CH0/CH1 1 1 0 0 0 1 1 ... 1 9/8 • VREF 0 CH0/CH1 1 1 0 0 0 1 1 ... 1 VREF + 1LSB 0 CH0/CH1 1 1 0 0 0 0 0 ... 0 VREF 0 CH0/CH1 1 0 1 1 1 1 1 ... 1 3/4VREF + 1LSB 0 CH0/CH1 1 0 1 1 0 0 0 ...
PAGE 14
LTC2421/LTC2422 U W U U APPLICATIO S I FOR ATIO synchronous 3-wire interface. During the conversion and sleep states, this interface can be used to assess the converter status and during the data output state, it is used to read the conversion result. –60 –70 REJECTION (dB) –80 –90 –100 Serial Clock Input/Output (SCK) –110 The serial clock signal present on SCK (Pin 9) is used to synchronize the data transfer. Each bit of data is shifted out the SDO pin on the falling edge of the serial clock.
PAGE 15
LTC2421/LTC2422 U W U U APPLICATIO S I FOR ATIO interface with other devices. If CS is LOW during the convert or sleep state, SDO will output EOC. If CS is LOW during the conversion phase, the EOC bit appears HIGH on the SDO pin. Once the conversion is complete, EOC goes LOW. The device remains in the sleep state until the first rising edge of SCK occurs while CS = 0. While in the sleep state, the device is in a LOW power state if CS is HIGH.
PAGE 16
LTC2421/LTC2422 U W U U APPLICATIO S I FOR ATIO At the conclusion of the data cycle, CS may remain LOW and EOC monitored as an end-of-conversion interrupt. Alternatively, CS may be driven HIGH setting SDO to Hi-Z. As described above, CS may be pulled LOW at any time in order to monitor the conversion status. CS HIGH anytime between the first rising edge and the 24th falling edge of SCK, see Figure 7.
PAGE 17
LTC2421/LTC2422 U W U U APPLICATIO S I FOR ATIO goes HIGH (EOC = 1) indicating a new conversion has begun. External Serial Clock, 2-Wire I/O This timing mode utilizes a 2-wire serial I/O interface. The conversion result is shifted out of the device by an externally generated serial clock (SCK) signal, see Figure 8. CS may be permanently tied to ground (Pin 6), simplifying the user interface or isolation barrier.
PAGE 18
LTC2421/LTC2422 U W U U APPLICATIO S I FOR ATIO VCC 2.7V TO 5.5V VCC 1µF 1 VCC FO 10 LTC2422 REFERENCE VOLTAGE ZSSET + 0.1V TO VCC ANALOG INPUT RANGE ZSSET – 0.12VREF TO FSSET + 0.
PAGE 19
LTC2421/LTC2422 U W U U APPLICATIO S I FOR ATIO VCC 2.7V TO 5.5V VCC 1µF 1 VCC FO 10 LTC2422 REFERENCE VOLTAGE ZSSET + 0.1V TO VCC ANALOG INPUT RANGE ZSSET – 0.12VREF TO FSSET + 0.
PAGE 20
LTC2421/LTC2422 U W U U APPLICATIO S I FOR ATIO VCC 2.7V TO 5.5V VCC 1µF 1 VCC FO 10 LTC2422 2 REFERENCE VOLTAGE ZSSET + 0.1V TO VCC 3 ANALOG INPUT RANGE ZSSET – 0.12VREF TO FSSET + 0.
PAGE 21
LTC2421/LTC2422 U W U U APPLICATIO S I FOR ATIO VCC 2.7V TO 5.5V VCC 1µF 1 VCC FO = INTERNAL OSC/50Hz REJECTION = EXTERNAL CLOCK SOURCE = INTERNAL OSC/60Hz REJECTION 10 LTC2422 REFERENCE VOLTAGE ZSSET + 0.1V TO VCC 2 3 ANALOG INPUT RANGE ZSSET – 0.12VREF TO FSSET + 0.
PAGE 22
LTC2421/LTC2422 U W U U APPLICATIO S I FOR ATIO resistance ground plane through a minimum length trace. The use of multiple via holes is recommended to further reduce the connection resistance. In an alternative configuration, the GND pin of the converter can be the single-point-ground in a single point grounding system.
PAGE 23
LTC2421/LTC2422 U W U U APPLICATIO S I FOR ATIO Input Current (VIN) If complete settling occurs on the input, conversion results will be uneffected by the dynamic input current. If the settling is incomplete, it does not degrade the linearity performance of the device. It simply results in an offset/ full-scale shift, see Figure 17. To simplify the analysis of input dynamic current, two separate cases are assumed: large capacitance at VIN (CIN > 0.01µF) and small capacitance at VIN (CIN < 0.01µF).
PAGE 24
LTC2421/LTC2422 U W U U APPLICATIO S I FOR ATIO 60 10 FULL-SCALE ERROR (ppm) 0 FULL-SCALE ERROR (ppm) CVREF = 22µF CVREF = 10µF CVREF = 1µF CVREF = 0.1µF CVREF = 0.01µF CVREF = 0.001µF 50 –10 CIN = 0pF CIN = 100pF CIN = 1000pF –20 –30 VCC = 5V VREF = 5V VIN = 5V TA = 25°C –40 –50 1 10 CIN = 0.
PAGE 25
LTC2421/LTC2422 U W U U APPLICATIO S I FOR ATIO 0.015ppm/Ω independent of capacitance at VREF, see Figure 26. –20 –40 REJECTION (dB) In addition to the dynamic reference current, the VREF ESD protection diodes have a temperature dependent leakage current. This leakage current, nominally 1nA (±10nA max), results in a fixed full-scale shift of 10µV for a 10k source resistance. 0 –60 –80 –100 –120 10 CVREF = 22µF CVREF = 10µF CVREF = 1µF CVREF = 0.1µF CVREF = 0.01µF CVREF = 0.
PAGE 26
LTC2421/LTC2422 U W U U APPLICATIO S I FOR ATIO nummeas = nummeas + c1% LOCATE 5, 21: PRINT "CHANNEL 1": LOCATE 5, 2: PRINT "CHANNEL 0" LOCATE 2, 2: PRINT "Scan#="; nummeas; " "; DATE$; " "; TIME$; FOR n% = port TO port + 7: OUT n%, 0: NEXT n%: ’Init UART regs OUT mcr%, c0%: 'Initialize SCLK=0 CLOSE #1: DEF SEG = 0: RETURN ’-------------------------------------- k1 = km: d2400 = 0: chan% = c0%: signneg% = c0% 2000 ’SUB read MSR AND RETURN data dfrm% INTERFACE FOR bita% = 31 TO 0 STEP -1: v31 = 1
PAGE 27
LTC2421/LTC2422 U W U U APPLICATIO S I FOR ATIO resistance RP1 in series with the half-bridge sensor are removed by the FSSET input to the ADC. The absolute fullscale output of the ADC (data out = FFFFFHEX ) will occur at VIN = VB = FSSET, see Figure 31. Similarly, the offset errors due to RP2 are removed by the ground sense input ZSSET. The absolute zero output of the ADC (data out = 00000HEX) occurs at VIN = VA = ZSSET.
PAGE 28
LTC2421/LTC2422 U W U U APPLICATIO S I FOR ATIO The selection between CH0 and CH1 is automatic. Initially, after power-up, a conversion is performed on CH0. For each subsequent conversion, the input channel selection is alternated. Embedded within the serial data output is a status bit indicating which channel corresponds to the conversion result. If the conversion was performed on CH0, this bit (Bit 22) is LOW and is HIGH if the conversion was performed on CH1 (see Figure 33).
PAGE 29
LTC2421/LTC2422 U W U U APPLICATIO S I FOR ATIO The absolute accuracy (less than 10 ppm total error) of the LTC2422 enables extremely accurate measurement of small signals sitting on large voltages. Each of the two pseudo differential measurements performed by the LTC2422 is absolutely accurate independent of the common mode voltage output from the bridge.
PAGE 30
LTC2421/LTC2422 U W U U APPLICATIO S I FOR ATIO from the time power is applied to VCC1 until the LT1761’s output has reached 5V, is approximately 1ms. Below 4.2V, the LTC1535’s driver outputs Y and Z are in a high impedance state, allowing the 1kΩ pull-down to define the logic state at SCK. When the LTC2422 first becomes active, it samples SCK; a logic “0” provided by the 1kΩ pull-down invokes the external serial clock mode.
PAGE 31
LTC2421/LTC2422 W PACKAGE I FOR ATIO U U MS Package 10-Lead Plastic MSOP (Reference LTC DWG # 05-08-1661) 0.889 ± 0.127 (.035 ± .005) 5.23 (.206) MIN 3.2 – 3.45 (.126 – .136) 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 0.50 3.05 ± 0.38 (.0197) (.0120 ± .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) 0.497 ± 0.076 (.0196 ± .003) REF 10 9 8 7 6 3.00 ± 0.102 (.118 ± .004) NOTE 4 4.88 ± 0.10 (.192 ± .004) DETAIL “A” 0° – 6° TYP GAUGE PLANE 1 2 3 4 5 0.53 ± 0.01 (.021 ± .006) DETAIL “A” 1.10 (.
PAGE 32
LTC2421/LTC2422 U TYPICAL APPLICATIO convert either the thermal couple output or the thermistor cold junction output. After each conversion, the devices enter their sleep state and wait for the SCK signal before clocking out data and beginning the next conversion. Figure 37 shows the block diagram of a demo circuit (contact LTC for a demonstration) of a multichannel isolated temperature measurement system. This circuit decodes an address to select which LTC2422 receives a 24-bit burst of SCK signal.