Datasheet

16
LTC2421/LTC2422
24212f
APPLICATIO S I FOR ATIO
WUUU
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Alternatively, CS may be driven HIGH setting SDO to Hi-Z.
As described above, CS may be pulled LOW at any time in
order to monitor the conversion status.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
Figure 6. External Serial Clock, Single Cycle Operation
V
CC
F
O
FS
SET
ZS
SET
SCK
CH1 SDO
GND
CS
REFERENCE VOLTAGE
ZS
SET
+ 0.1V TO V
CC
0V TO FS
SET
– 100mV
CH0
= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION
1µF
110
9
8
7
6
2
3
4
5
2.7V TO 5.5V
LTC2422
V
CC
3-WIRE
SERIAL I/O
ANALOG INPUT RANGE
ZS
SET
– 0.12V
REF
TO
FS
SET
+ 0.12V
REF
(V
REF
= FS
SET
– ZS
SET
)
EOC CH0/CH1
BIT 23
SDO
SCK
(EXTERNAL)
CS
TEST EOC
MSB LSB
20
EXRSIG
BIT 0BIT 4BIT 19 BIT 18BIT 20BIT 21BIT 22
SLEEP DATA OUTPUT CONVERSION
24212 F06
CONVERSION
Hi-ZHi-ZHi-Z
TEST EOCTEST EOC
CS HIGH anytime between the first rising edge and the
24th falling edge of SCK, see Figure 7. On the rising edge
of CS, the device aborts the data output state and imme-
diately initiates a new conversion. This is useful for sys-
tems not requiring all 24 bits of output data, aborting an
invalid conversion cycle or synchronizing the start of a
conversion.
Figure 7. External Serial Clock, Reduced Data Output Length
V
CC
F
O
FS
SET
ZS
SET
SCK
CH1 SDO
GND
CS
REFERENCE VOLTAGE
ZS
SET
+ 0.1V TO V
CC
0V TO FS
SET
– 100mV
CH0
= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION
1µF
110
9
8
7
6
2
3
4
5
2.7V TO 5.5V
LTC2422
V
CC
3-WIRE
SERIAL I/O
ANALOG INPUT RANGE
ZS
SET
– 0.12V
REF
TO
FS
SET
+ 0.12V
REF
(V
REF
= FS
SET
– ZS
SET
)
SDO
SCK
(EXTERNAL)
CS
DATA OUTPUT
CONVERSIONSLEEP SLEEP
TEST EOC TEST EOC
DATA OUTPUT
Hi-Z Hi-ZHi-Z
CONVERSION
24212 F07
MSBEXRSIG
BIT 8BIT 19 BIT 9BIT 20BIT 21BIT 22
EOC CH0/CH1
BIT 23
BIT 0
EOC
Hi-Z
TEST EOC