LTC2430/LTC2431 20-Bit No Latency ∆ΣTM ADCs with Differential Input and Differential Reference U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO Low Supply Current (200µA in Conversion Mode and 4µA in Autosleep Mode) Differential Input and Differential Reference with GND to VCC Common Mode Range 3ppm INL, No Missing Codes 10ppm Full-Scale Error and 1ppm Offset 0.56ppm Noise, 20.8 ENOBs No Latency: Digital Filter Settles in a Single Cycle.
LTC2430/LTC2431 W W W AXI U U ABSOLUTE RATI GS (Notes 1, 2) Supply Voltage (VCC) to GND .......................– 0.3V to 7V Analog Input Pins Voltage to GND ......................................... – 0.3V to (VCC + 0.3V) Reference Input Pins Voltage to GND ......................................... – 0.3V to (VCC + 0.3V) Digital Input Voltage to GND ........ – 0.3V to (VCC + 0.3V) Digital Output Voltage to GND ..... – 0.3V to (VCC + 0.3V) Operating Temperature Range LTC2430C/LTC2431C ................
LTC2430/LTC2431 U CO VERTER CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4) PARAMETER CONDITIONS Input Common Mode Rejection DC 2.5V ≤ REF + ≤ V MIN TYP ● 110 120 Input Common Mode Rejection 60Hz ±2% 2.5V ≤ REF+ ≤ VCC, REF – = GND, GND ≤ IN – = IN + ≤ 5V, (Notes 5, 7) ● 140 dB Input Common Mode Rejection 50Hz ±2% 2.
LTC2430/LTC2431 U U DIGITAL I PUTS A D DIGITAL OUTPUTS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) SYMBOL PARAMETER CONDITIONS VIH High Level Input Voltage CS, FO 2.7V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 3.3V ● MIN VIL Low Level Input Voltage CS, FO 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V ● VIH High Level Input Voltage SCK 2.7V ≤ VCC ≤ 5.5V (Note 9) 2.7V ≤ VCC ≤ 3.
LTC2430/LTC2431 WU TI I G CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) SYMBOL PARAMETER CONDITIONS MIN fEOSC External Oscillator Frequency Range ● tHEO External Oscillator High Period ● tLEO External Oscillator Low Period ● 0.
LTC2430/LTC2431 U W TYPICAL PERFOR A CE CHARACTERISTICS Total Unadjusted Error (VCC = 5V, VREF = 5V) Total Unadjusted Error (VCC = 5V, VREF = 2.5V) 85°C 1 0 –1 –45°C –2 VCC = 5V 4 VREF = 2.5V VINCM = VINCM = 1.25V 3 F = GND O 2 0 25°C –1 85°C –2 –3 –4 –4 2 –45°C 1 –3 –5 –2.5 –2 –1.5 –1 – 0.5 0 0.5 1 1.5 INPUT VOLTAGE (V) VCC = 2.7V 15 VREF = 2.5V VINCM = VINCM = 1.25V 10 FO = GND INL (ppm OF VREF) 85°C –2 VCC = 5V –3 V REF = 5V –4 VINCM = VINCM = 2.5V FO = GND –5 –2.5 –2 –1.5 –1 – 0.
LTC2430/LTC2431 U W TYPICAL PERFOR A CE CHARACTERISTICS VCC = 5V REF + = 5V REF – = GND VIN = 0V VINCM = GND FO = GND TA = 25°C 3.0 2.8 3.2 3.0 2.8 2.6 –1 1 0 3 2 VINCM (V) 4 5 2.4 –50 6 2.4 –25 75 0 25 50 TEMPERATURE (°C) 1.0 0.8 0.8 0.6 0.4 0.2 0 –0.6 –0.8 –1.0 1 0 3 2 VREF (V) 4 –1 5 1 0 4 0.2 0 –0.8 –1.0 REF + = VCC REF – = GND VIN = 0V VINCM = GND FO = GND TA = 25°C 2.7 3.1 3.5 –0.8 3 2 VINCM (V) 4 5 –1.0 –45 –30 –15 6 5.1 5.
LTC2430/LTC2431 U W TYPICAL PERFOR A CE CHARACTERISTICS Full-Scale Error vs VREF PSRR vs Frequency at VCC 10 +FS ERROR 4 5 0 –5 –FS ERROR –10 –15 3 +FS ERROR 2 VREF = 2.5V REF – = GND FO = GND VINCM = 0.5VREF TA = 25°C 1 0 –1 –2 –20 –40 0.5 1 1.5 2 2.5 3 VREF (V) 3.5 4 4.5 2.7 5 3.1 3.5 3.9 4.3 VCC (V) 5.1 4.7 24301 G22 PSRR vs Frequency at VCC 0 0 VCC = 4.1VDC REF+ = 2.
LTC2430/LTC2431 U U U PI FU CTIO S (LTC2430) GND (Pins 1, 7, 8, 9, 10, 15, 16): Ground. Multiple ground pins internally connected for optimum ground current flow and VCC decoupling. Connect each one of these pins to a ground plane through a low impedance connection. All seven pins must be connected to ground for proper operation. VCC (Pin 2): Positive Supply Voltage. Bypass to GND with a 10µF tantalum capacitor in parallel with 0.1µF ceramic capacitor as close to the part as possible.
LTC2430/LTC2431 U U U PI FU CTIO S (LTC2431) SDO (Pin 8): Three-State Digital Output. During the Data Output period, this pin is used as the serial data output. When the chip select CS is HIGH (CS = VCC), the SDO pin is in a high impedance state. During the Conversion and Sleep periods, this pin is used as the conversion status output. The conversion status can be observed by pulling CS LOW. SCK (Pin 9): Bidirectional Digital Clock Pin.
LTC2430/LTC2431 U W U U APPLICATIO S I FOR ATIO CONVERTER OPERATION Converter Operation Cycle The LTC2430/LTC2431 are low power, delta-sigma analogto-digital converters with an easy-to-use 3-wire serial interface (see Figure 1). Their operation is made up of three states. The converters’ operating cycle begins with the conversion, followed by the low power sleep state and ends with the data output (see Figure 2).
LTC2430/LTC2431 U W U U APPLICATIO S I FOR ATIO Power-Up Sequence The LTC2430/LTC2431 automatically enter an internal reset state when the power supply voltage VCC drops below approximately 2V. This feature guarantees the integrity of the conversion result and of the serial interface mode selection. (See the 2-wire I/O sections in the Serial Interface Timing Modes section.
LTC2430/LTC2431 U W U U APPLICATIO S I FOR ATIO above +FS. If both Bit 21 and Bit 20 are LOW, the differential input voltage is below –FS. Bit 0 is the least significant bit (LSB). In order to shift the conversion result out of the device, CS must first be driven LOW. EOC is seen at the SDO pin of the device once CS is pulled LOW. EOC changes real time from HIGH to LOW at the completion of a conversion. This signal may be used as an interrupt for an external microcontroller.
LTC2430/LTC2431 U W U U APPLICATIO S I FOR ATIO Frequency Rejection Selection (FO) The LTC2430/LTC2431 internal oscillator provides better than 110dB normal mode rejection at the line frequency and all its harmonics for 50Hz ±2% or 60Hz ±2%. For 60Hz rejection, FO should be connected to GND while for 50Hz rejection the FO pin should be connected to VCC. The selection of 50Hz or 60Hz rejection can also be made by driving FO to an appropriate logic level.
LTC2430/LTC2431 U W U U APPLICATIO S I FOR ATIO Table 3. LTC2430/LTC2431 State Duration State Operating Mode CONVERT Internal Oscillator External Oscillator Duration FO = LOW (60Hz Rejection) 133ms, Output Data Rate ≤ 7.5 Readings/s FO = HIGH (50Hz Rejection) 160ms, Output Data Rate ≤ 6.
LTC2430/LTC2431 U W U U APPLICATIO S I FOR ATIO Table 4.
LTC2430/LTC2431 U W U U APPLICATIO S I FOR ATIO 2.7V TO 5.5V VCC 1µF VCC = 50Hz REJECTION = EXTERNAL OSCILLATOR = 60Hz REJECTION FO LTC2430/ LTC2431 REF + REFERENCE VOLTAGE 0.1V TO VCC SCK REF – ANALOG INPUT RANGE –0.5VREF TO 0.
LTC2430/LTC2431 U W U U APPLICATIO S I FOR ATIO 2.7V TO 5.5V VCC 1µF VCC = 50Hz REJECTION = EXTERNAL OSCILLATOR = 60Hz REJECTION FO LTC2430/ LTC2431 REF + REFERENCE VOLTAGE 0.1V TO VCC SCK REF – ANALOG INPUT RANGE –0.5VREF TO 0.5VREF 2-WIRE I/O IN + SDO IN – CS GND CS BIT 23 SDO BIT 22 EOC BIT 21 BIT 20 SIG MSB BIT 19 BIT 18 BIT 0 LSB SCK (EXTERNAL) CONVERSION DATA OUTPUT CONVERSION 2431 F07 Figure 7. External Serial Clock, CS = 0 Operation VCC 2.7V TO 5.
LTC2430/LTC2431 U W U U APPLICATIO S I FOR ATIO The serial data output pin (SDO) is Hi-Z as long as CS is HIGH. At any time during the conversion cycle, CS may be pulled LOW in order to monitor the state of the converter. Once CS is pulled LOW, SCK goes LOW and EOC is output to the SDO pin. EOC = 1 while a conversion is in progress and EOC = 0 if the device is in the sleep state.
LTC2430/LTC2431 U W U U APPLICATIO S I FOR ATIO internal pull-up is not available to restore SCK to a logic HIGH state. This will cause the device to exit the internal serial clock mode on the next falling edge of CS. This can be avoided by adding an external 10k pull-up resistor to the SCK pin or by never pulling CS HIGH when SCK is LOW. Whenever SCK is LOW, the LTC2430/LTC2431’s internal pull-up at pin SCK is disabled.
LTC2430/LTC2431 U W U U APPLICATIO S I FOR ATIO low power sleep state. The part remains in the sleep state a minimum amount of time (1/2 the internal SCK period) then immediately begins outputting data. The data output cycle begins on the first rising edge of SCK and ends after the 24th rising edge. Data is shifted out the SDO pin on each falling edge of SCK. The internally generated serial clock is output to the SCK pin. This signal may be used to shift the conversion result into external circuitry.
LTC2430/LTC2431 U W U U APPLICATIO S I FOR ATIO between the FO signal trace and the input/reference signals. When the FO signal is parallel terminated near the converter, substantial AC current is flowing in the loop formed by the FO connection trace, the termination and the ground return path. Thus, perturbation signals may be inductively coupled into the converter input and/or reference.
LTC2430/LTC2431 U W U U APPLICATIO S I FOR ATIO For relatively small values of input capacitance (C IN < 0.01µF), the voltage on the sampling capacitor settles almost completely and relatively large values for the source impedance result in only small errors. Such values for CIN will deteriorate the converter offset and gain performance without significant benefits of signal filtering and the user is advised to avoid them.
LTC2430/LTC2431 U W U U APPLICATIO S I FOR ATIO The typical +FS and –FS errors as a function of the sum of the source resistance seen by IN+ and IN– for large values of CIN are shown in Figure 15. In addition to this gain error, an offset error term may also appear. The offset error is proportional with the mismatch between the source impedance driving the two input pins IN+ and IN– and with the difference between the input and reference common mode voltages.
LTC2430/LTC2431 U W U U APPLICATIO S I FOR ATIO Reference Current In a similar fashion, the LTC2430 or LTC2431 samples the differential reference pins REF+ and REF– transfering small amount of charge to and from the external driving circuits thus producing a dynamic reference current. This current does not change the converter offset, but it may degrade the gain and INL performance. The effect of this current can be analyzed in the same two distinct situations.
LTC2430/LTC2431 U W U U APPLICATIO S I FOR ATIO 0 15 CREF = 0.01µF 12 9 –20 CREF = 1µF, 10µF CREF = 0.1µF –30 –40 –50 –60 VCC = 5V VREF + = 5V VREF – = GND VIN + = 3.75V VIN – = 1.25V FO = GND TA = 25°C Figure 18a. +FS Error vs RSOURCE at REF+ or REF– (Large CREF) –FS ERROR (ppm) 50 40 0 –3 –6 –12 2431 F18a VCC = 5V VREF + = 5V VREF – = GND VIN + = 1.25V VIN – = 3.
LTC2430/LTC2431 U W U U APPLICATIO S I FOR ATIO Output Data Rate When using the internal oscillator, the LTC2430/LTC2431 can produce up to 7.5 readings per second with a notch frequency of 60Hz (FO = LOW) and 6.25 readings per second with a notch frequency of 50Hz (FO = HIGH). The actual output data rate will depend upon the length of the sleep and data output phases which are controlled by the user and which can be made insignificantly short.
LTC2430/LTC2431 U W U U APPLICATIO S I FOR ATIO OFFSET ERROR (ppm OF VREF) 5 VINCM = VREFCM VCC = VREF = 5V VIN = 0V FO = EXT OSC 9 8 7 6 5 4 TA = 85°C 3 TA = 25°C 2 TA = 85°C –5 –10 –15 –20 VINCM = VREFCM VCC = VREF = 5V FO = EXT OSC –25 1 0 TA = 25°C 0 +FS ERROR (ppm OF VREF) 10 –30 0 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2431 F21 2431 F20 Figure 20.
LTC2430/LTC2431 U W U U APPLICATIO S I FOR ATIO 22 VCC = VREF = 5V 21 20 19 VCC = 2.7V VREF = 2.5V 18 VINCM = VREFCM 17 VIN = 0V FO = EXT OSC REF – = GND 16 TA = 25°C RES = LOG2(VREF/NOISERMS) 15 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) RESOLUTION (BITS) RESOLUTION (BITS) 21 22 20 VCC = VREF = 5V 19 18 VCC = 2.7V VINCM = VREFCM VREF = 2.
LTC2430/LTC2431 U W U U APPLICATIO S I FOR ATIO If the FO pin is driven by an external oscillator of frequency fEOSC, Figure 29 can still be used for noise calculation if the x-axis is scaled by fEOSC/153600. For large values of the ratio fEOSC/153600, the Figure 29 plot accuracy begins to decrease, but in the same time the LTC2430/LTC2431 noise floor rises and the noise contribution of the driving amplifiers lose significance.
LTC2430/LTC2431 U W U U 0 0 –10 –10 INPUT NORMAL MODE REJECTION (dB) INPUT NORMAL MODE REJECTION (dB) APPLICATIO S I FOR ATIO –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 fN 2fN 3fN 4fN 5fN 6fN 7fN INPUT SIGNAL FREQUENCY (Hz) –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 250fN 252fN 254fN 256fN 258fN 260fN 262fN INPUT SIGNAL FREQUENCY (Hz) 8fN 2431 F32 2431 F33 Figure 32. Input Normal Mode Rejection MEASURED DATA CALCULATED DATA –20 –40 VCC = 5V VREF = 5V VINCM = 2.
LTC2430/LTC2431 U W U U APPLICATIO S I FOR ATIO VIN(P-P) = 5V VIN(P-P) = 7.5V (150% OF FULL SCALE) –20 –40 VCC = 5V VREF = 5V VINCM = 2.5V FO = GND TA = 25°C – 60 –80 –100 –120 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 INPUT FREQUENCY (Hz) 0 NORMAL MODE REJECTION (dB) NORMAL MODE REJECTION (dB) 0 VIN(P-P) = 5V VIN(P-P) = 7.5V (150% OF FULL SCALE) –20 –40 VCC = 5V VREF = 5V VINCM = 2.
LTC2430/LTC2431 U W U U APPLICATIO S I FOR ATIO where measurement speed is not of the utmost importance. For many applications where large vessels are weighed, the average weight over an extended period of time is of concern and short term weight is not readily determined due to movement of contents, or mechanical resonance.
LTC2430/LTC2431 U W U U APPLICATIO S I FOR ATIO practice in earlier generations of load-cell interfaces, however the accuracy of the LTC2430/LTC2431 changes the rationale. Achieving high gain accuracy and linearity at higher gains may prove difficult, while providing little benefit in terms of noise reduction. applications where the gain setting resistor can be made to match the temperature coefficient of the strain gauges.
LTC2430/LTC2431 U W U U APPLICATIO S I FOR ATIO single variable element bridges, the nonlinearity of the half bridge output can be eliminated completely; if the reference arm of the bridge is used as the reference to the ADC, as shown in Figure 41. The LTC2430/LTC2431 can accept inputs up to 1/2 VREF. Hence, the reference resistor R1 must be at least 2× the highest value of the variable resistor. In the case of 100Ω platinum RTD’s, this would suggest a value of 800Ω for R1.
LTC2430/LTC2431 U W U U APPLICATIO S I FOR ATIO The circuit shown in Figure 42 shows a more rigorous example of Figure 41, with increased noise suppression and more protection for remote applications. drift translates into 0.05ppm/°C gain error. Simpler alternatives, with the amplifiers providing gain using resistor arrays for feedback, can produce results that are similar to bridge sensing schemes via attenuators.
LTC2430/LTC2431 U W U U APPLICATIO S I FOR ATIO temperature) will produce a worst-case error of –180ppm at a noise gain of 3, such as would be encountered in an inverting gain of 2, to produce –10V from a 5V reference. of the A/D and multiplexer in normal operation, some thought should be given to fault conditions that could result in full excitation voltage at the inputs to the multiplexer or ADC.
LTC2430/LTC2431 U W U U APPLICATIO S I FOR ATIO 15V + 20Ω Q1 2N3904 1/2 LT1112 1 – C1 0.1µF 22Ω 5V 3 + 2 LT1236-5 C3 47µF C1 0.1µF RN1 10k 10V 1 5V 2 RN1 10k 350Ω BRIDGE TWO ELEMENTS VARYING 3 VCC LTC2430/ LTC2431 REF + 4 REF – IN + –5V IN – 8 RN1 10k 5 7 C2 0.1µF 20Ω 7 15V RN1 IS CADDOCK T914 10K-010-02 8 – 1/2 LT1112 4 –15V GND 6 33Ω ×2 Q2, Q3 2N3906 ×2 RN1 10k –15V + 6 5 2431 F45 Figure 45.
LTC2430/LTC2431 U PACKAGE DESCRIPTIO GN Package 16-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) .189 – .196* (4.801 – 4.978) .045 ±.005 .009 (0.229) REF 16 15 14 13 12 11 10 9 .254 MIN .150 – .165 .229 – .244 (5.817 – 6.198) .0165 ± .0015 .150 – .157** (3.810 – 3.988) .0250 TYP RECOMMENDED SOLDER PAD LAYOUT 1 .015 ± .004 × 45° (0.38 ± 0.10) .007 – .0098 (0.178 – 0.249) 2 3 4 5 6 .053 – .068 (1.351 – 1.727) 7 8 .004 – .0098 (0.102 – 0.249) 0° – 8° TYP .016 – .
LTC2430/LTC2431 U TYPICAL APPLICATIO SUPPLY VOLTAGE RANGE: (VOUT + 0.25V) TO 20V LT1790 VOUT 4.7µF 6 4 LT1790 1 0.1µF 2 VCC 0.1µF VCC = INTERNAL OSC/50Hz REJECTION = EXTERNAL CLOCK SOURCE = INTERNAL OSC/60Hz REJECTION FO LTC2431 REF + SCK REF – ANALOG INPUT RANGE –0.5VREF TO 0.5VREF Relative Size of Components IN + SDO IN – CS 3-WIRE SPI INTERFACE GND 24301 TA05 THE LT1790 IS AVAILABLE WITH 1.25V, 2.048V, 2.5V, 3V, 3.3V, 4.