Datasheet

ManualsBrandsLinear Technology ManualsADC - Analog to DigitalA/D Converter IC 24bit SSOP-Delta Sigma

LTC2440

2440fe

For more information www.linear.com/LTC2440

2440 TA01

REFERENCE VOLTAGE

0.1V TO V

ANALOG INPUT

–0.5V

REF

TO 0.5V

REF

3-WIRE

SPI INTERFACE

6.9Hz, 200nV NOISE,

50/60Hz REJECTION

880Hz OUTPUT RATE,

2µV NOISE

10-SPEED SERIAL

PROGRAMMABLE

4.5V TO 5.5V

BUSY

REF

SCK

–

SDO

GND

EXT

SDI

LTC2440

REF

–

TYPICAL APPLICATION

FEATURES

APPLICATIONS

DESCRIPTION

24-Bit High Speed

Differential

∆∑

ADC with

Selectable Speed/Resolution

The LTC

2440 is a high speed 24-bit No Latency ∆∑

ADC with 5ppm INL and 5µV offset. It uses a proprietary

delta-sigma architecture enabling variable speed and reso

lution with no latency. Ten speed/resolution combinations

(6.9Hz/200nV

RMS

to 3.5kHz/25µV

RMS

) are programmed

through a simple serial interface. Alternatively, by tying a

single pin HIGH or LOW, a fast (880Hz/2µV

RMS

) or ultralow

noise (6.9Hz, 200nV

RMS

, 50/60Hz rejection) speed/reso-

lution combination can be easily selected. The accuracy

(offset, full-scale, linearity, drift) and power dissipation

are independent of the speed selected. Since there is no

latency

, a speed/resolution change may be made between

conversions with no degradation in performance.

Following each conversion cycle, the LTC2440 automati

cally enters a low power sleep state. Power dissipation

may be reduced by increasing the duration of this sleep

state. For example, running at the 3.5kHz conversion speed

but reading data at a 100Hz rate draws 240µA average

current (1.1mW) while reading data at a 7Hz output rate

draws only 25µA (125µW).The LTC2440 communicates

through a flexible 3-wire or 4-wire digital interface that is

compatible with the LTC2410 and is available in a narrow

16-lead SSOP package.

Simple 24-Bit 2-Speed Acquisition System

Up to 3.5kHz Output Rate (External f

)

Selectable Speed/Resolution

2µV

RMS

Noise at 880Hz Output Rate

200nV

RMS

Noise at 6.9Hz Output Rate with

Simultaneous 50/60Hz Rejection

0.0005% INL, No Missing Codes

Autosleep Enables 20µA Operation at 6.9Hz

<5µV Offset (4.5V < V

< 5.5V, –40°C to 85°C)

Differential Input and Differential Reference with

GND to V

Common Mode Range

No Latency, Each Conversion is Accurate Even After

an Input Step

Internal Oscillator—No External Components

Pin Compatible with the LTC2410

24-Bit ADC in Narrow 16-Lead SSOP Package

High Speed Multiplexing

Weight Scales

Auto Ranging 6-Digit DVMs

Direct Temperature Measurement

High Speed Data Acquisition

RMS Noise vs Speed

CONVERSION RATE (Hz)

0.1

RMS NOISE (µV)

100

10 100

2440 TA02

1000 10000

= 5V

REF

= 5V

= V

–

= 0V

2µV AT 880Hz

200nV AT 6.9Hz

(50/60Hz REJECTION)

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

No Latency ∆∑ and SoftSpan are trademarks of Linear Technology Corporation. All other

trademarks are the property of their respective owners.

Downloaded from Arrow.com.

Summary of content (30 pages)

PAGE 1
LTC2440 24-Bit High Speed Differential ∆∑ ADC with Selectable Speed/Resolution FEATURES n n n n n n n n n n n n DESCRIPTION Up to 3.5kHz Output Rate (External fO) Selectable Speed/Resolution 2µVRMS Noise at 880Hz Output Rate 200nVRMS Noise at 6.9Hz Output Rate with Simultaneous 50/60Hz Rejection 0.0005% INL, No Missing Codes Autosleep Enables 20µA Operation at 6.9Hz <5µV Offset (4.5V < VCC < 5.
PAGE 2
LTC2440 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Notes 1,2) Supply Voltage (VCC) to GND........................ –0.3V to 6V Analog Input Pins Voltage to GND.......................................–0.3V to (VCC + 0.3V) Reference Input Pins Voltage to GND.......................................–0.3V to (VCC + 0.3V) Digital Input Voltage to GND..........–0.3V to (VCC + 0.3V) Digital Output Voltage to GND........–0.3V to (VCC + 0.3V) Operating Temperature Range LTC2440C .....................................
PAGE 3
LTC2440 ANALOG INPUT AND REFERENCE The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) SYMBOL PARAMETER IN + Absolute/Common Mode IN + Voltage CONDITIONS l GND – 0.3V VCC + 0.3V V IN – Absolute/Common Mode IN – Voltage l GND – 0.3V VCC + 0.3V V VIN Input Differential Voltage Range (IN + – IN –) l –VREF / 2 VREF / 2 V REF + Absolute/Common Mode REF + Voltage l 0.
PAGE 4
LTC2440 POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) SYMBOL PARAMETER VCC ICC Supply Voltage CONDITIONS MIN l Supply Current Conversion Mode Sleep Mode CS = 0V (Note 7) CS = VCC (Note 7) TYP 4.5 8 8 l l MAX UNITS 5.
PAGE 5
LTC2440 TYPICAL PERFORMANCE CHARACTERISTICS –5 –10 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 VIN (V) 1.5 2 VINCM = 2.5V fO = GND TA = 25°C 0 –5 –10 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 VIN (V) 2.5 2440 G01 Integral Nonlinearity fOUT = 440Hz VCC = 5V VREF = 5V VREF+ = 5V – 5 VREF = GND 10 VINCM = 2.5V fO = GND TA = 25°C 0 –5 –10 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 VIN (V) 1.5 2 VCC = 5V VREF = 5V VREF+ = 5V – 5 VREF = GND VINCM = 2.5V fO = GND TA = 25°C 0 –5 –10 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 VIN (V) 2.
PAGE 6
LTC2440 TYPICAL PERFORMANCE CHARACTERISTICS 10.0 VINCM = 2.5V fO = GND TA = 25°C 0 –5 –10 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 VIN (V) 1.5 2 7.5 –2.5V ≤ VIN ≤ 2.5V VINCM = 2.5V fO = GND TA = 25°C 2.5 0 500 1000 1500 2000 2500 3000 3500 CONVERSION RATE (Hz) TA = –55°C INL ERROR (ppm OF VREF) INL ERROR (ppm OF VREF) 10 VINCM = 1.25V OSR = 32768 fO = GND TA = 125°C 0 TA = 25°C –5 –10 –1.25 –0.75 0.25 –0.25 VIN (V) 0.
PAGE 7
LTC2440 TYPICAL PERFORMANCE CHARACTERISTICS Negative Full-Scale Error vs Temperature 10 4.5V 5 VCC = 4.5V VREF = 4.5V VREF+ = 4.5V VREF– = GND VINCM = 2.25V OSR = 32768 fO = GND VCC = 5.5V, 5V VREF = 5V VREF+ = 5V VREF– = GND VINCM = 2.5V OSR = 32768 fO = GND 0 –5 5.5V –10 5V –15 –20 –55 –25 35 5 65 TEMPERATURE (°C) 15 10 5 5.5V 0 –5 4.5V 5V –10 –15 –20 –55 125 95 5.0 –25 VCC = 4.5V VREF = 4.5V VREF+ = 4.5V VREF– = GND VINCM = 2.25V OSR = 32768 fO = GND VCC = 5.
PAGE 8
LTC2440 PIN FUNCTIONS GND (Pins 1, 8, 9, 16): Ground. Multiple ground pins internally connected for optimum ground current flow and VCC decoupling. Connect each one of these pins to a ground plane through a low impedance connection. All four pins must be connected to ground for proper operation. VCC (Pin 2): Positive Supply Voltage. Bypass to GND (Pin 1) with a 10µF tantalum capacitor in parallel with 0.1µF ceramic capacitor as close to the part as possible.
PAGE 9
LTC2440 FUNCTIONAL BLOCK DIAGRAM INTERNAL OSCILLATOR VCC GND IN+ IN– AUTOCALIBRATION AND CONTROL fO (INT/EXT) + – SDO ADC SCK SERIAL INTERFACE DECIMATING FIR CS SDI BUSY DAC 2440 F01 EXT + – REF+ REF– Figure 1. Functional Block Diagram TEST CIRCUITS VCC 1.69k SDO 1.
PAGE 10
LTC2440 APPLICATIONS INFORMATION Initially, the LTC2440 performs a conversion. Once the conversion is complete, the device enters the sleep state. While in this sleep state, power consumption is reduced below 10µA. The part remains in the sleep state as long as CS is HIGH. The conversion result is held indefinitely in a static shift register while the converter is in the sleep state. Once CS is pulled LOW, the device begins outputting the conversion result. There is no latency in the conversion result.
PAGE 11
LTC2440 APPLICATIONS INFORMATION the converter indicates the overrange or the underrange condition using distinct output codes. Output Data Format The LTC2440 serial output data stream is 32-bits long. The first 3-bits represent status information indicating the sign and conversion state. The next 24-bits are the conversion result, MSB first. The remaining 5-bits are sub LSBs beyond the 24-bit level that may be included in averaging or discarded without loss of resolution.
PAGE 12
LTC2440 APPLICATIONS INFORMATION shifted out on the falling edge of the 31st SCK and may be latched on the rising edge of the 32nd SCK pulse. On the falling edge of the 32nd SCK pulse, SDO goes HIGH indicating the initiation of a new conversion cycle. This bit serves as EOC (Bit 31) for the next conversion cycle. Table 2 summarizes the output data format. As long as the voltage on the IN+ and IN – pins is maintained within the –0.3V to (VCC + 0.
PAGE 13
LTC2440 APPLICATIONS INFORMATION Chip Select Input (CS) Serial Data Input (SDI)—Serial Input Speed Selection The active LOW chip select, CS (Pin 11), is used to test the conversion status and to enable the data output transfer as described in the previous sections. SDI may also be programmed by a serial input data stream under control of SCK during the data output cycle, see Figure 4. One of ten speed/resolution ranges (from 6.9Hz/200nVRMS to 3.5kHz/21µVRMS) may be selected, see Table 3.
PAGE 14
LTC2440 APPLICATIONS INFORMATION CS SCK SDI Hi-Z SDO OSR4* OSR3 OSR2 OSR1 OSR0 BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 EOC “0” SIG MSB BIT 26 BIT 25 BIT 1 BIT 0 Hi-Z LSB BUSY 2440 F04 *OSR4 BIT MUST BE AT FIRST SCK RISING EDGE DURING SERIAL DATA OUT CYCLE Figure 4. SDI Speed/Resolution Programming Table 3. SDI Speed/Resolution Programming OSR4 OSR3 OSR2 OSR1 OSR0 RMS NOISE ENOB OSR X 0 0 0 1 23µV 17 64 X 0 0 1 0 3.5µV 20 128 0 0 0 0 0 2µV 21.
PAGE 15
LTC2440 APPLICATIONS INFORMATION 4.5V TO 5.5V 1µF 2 REFERENCE VOLTAGE 0.1V TO VCC ANALOG INPUT RANGE –0.5VREF TO 0.
PAGE 16
LTC2440 APPLICATIONS INFORMATION 4.5V TO 5.5V 1µF 2 VCC BUSY LTC2440 3 REF+ fO 4 SCK REF– 5 SDO IN+ 6 CS IN– REFERENCE VOLTAGE 0.1V TO VCC ANALOG INPUT RANGE –0.5VREF TO 0.
PAGE 17
LTC2440 APPLICATIONS INFORMATION controller indicating the conversion result is ready. EOC = 1 (BUSY = 1) while the conversion is in progress and EOC = 0 (BUSY = 0) once the conversion enters the low power sleep state. On the falling edge of EOC/BUSY, the conversion result is loaded into an internal static shift register. The device remains in the sleep state until the first rising edge of SCK.
PAGE 18
LTC2440 APPLICATIONS INFORMATION on this first rising edge of SCK and concludes after the 32nd rising edge. Data is shifted out the SDO pin on each falling edge of SCK. The internally generated serial clock is output to the SCK pin. This signal may be used to shift the conversion result into external circuitry. EOC can be latched on the first rising edge of SCK and the last bit of the conversion result on the 32nd rising edge of SCK.
PAGE 19
LTC2440 APPLICATIONS INFORMATION 4.5V TO 5.5V 1µF 2 REFERENCE VOLTAGE 0.1V TO VCC ANALOG INPUT RANGE –0.5VREF TO 0.
PAGE 20
LTC2440 APPLICATIONS INFORMATION Table 5. OSR vs Notch Frequency (fN) with Internal Oscillator OSR NOTCH (fN) 64 28.16kHz 128 14.08kHz 256 7.04kHz 512 3.52kHz 1024 1.76kHz 2048 880Hz 4096 440Hz 8192 220Hz 16384 110Hz 32768* 55Hz the noise performance of the device is 200nVRMS with better than 80dB rejection of 50Hz ±2% and 60Hz ±2%. Since the OSR is large (32,768) the wide band rejection is extremely large and the antialiasing requirements are simple.
PAGE 21
LTC2440 APPLICATIONS INFORMATION The sample rate fS and NULL fN, my also be adjusted by driving the fO pin with an external oscillator. The sample rate is fS = fEOSC /5, where fEOSC is the frequency of the clock applied to fO. Combining a large OSR with a reduced sample rate leads to notch frequencies fN near DC while maintaining simple antialiasing requirements. A 100kHz clock applied to fO results in a NULL at 0.6Hz plus all harmonics up to 20kHz, see Figure 14.
PAGE 22
LTC2440 APPLICATIONS INFORMATION CONVERTER STATE SLEEP CONVERT SLEEP DATA OUT CONVERT SLEEP DATA OUT CS SUPPLY CURRENT 8µA 8mA 8µA 8µA 8mA 2440 F15 Figure 15. Reduced Power Timing Mode LTC2440 Input Structure Modern delta sigma converters have switched capacitor front ends that repeatedly sample the input voltage over some time period. The sampling process produces a small current pulse at the input and reference terminals as the capacitors are charged.
PAGE 23
LTC2440 APPLICATIONS INFORMATION Direct Connection to Low Impedance Sources Buffering the LTC2440 If the ADC can be located physically close to the sensor, it can be directly connected to sensors or other sources with impedances up to 350Ω with no other components required (see Figure 17). Many applications will require buffering, particularly where high impedance sources are involved or where the device being measured is located some distance from the LTC2440.
PAGE 24
LTC2440 APPLICATIONS INFORMATION fastest expected input signal. Figure 20 shows the large signal response of the circuit in Figure 19. 3. Measure noise performance of the complete circuit. A good technique is to build one amplifier for each input, even if only one will be used in the end application. Bias both amplifier outputs to midscale, with the inputs tied together.
PAGE 25
LTC2440 APPLICATIONS INFORMATION Table 6 lists the properties of the LTC2440 with various combinations of oversample ratio and clock frequency. Understanding these properties is the key to fine tuning the characteristics of the LTC2440 to the application. the modulator sample rate of 1.8MHz) exceeds 120dB. This is 8 times the maximum conversion rate.
PAGE 26
LTC2440 APPLICATIONS INFORMATION Example: If an amplifier (e.g. LT1219) driving the input of an LTC2440 has wideband noise of 33nV/√Hz, band-limited to 1.8MHz, the total noise entering the ADC input is: 33nV/√Hz • √1.8MHz = 44.3µV. When the ADC digitizes the input, its digital filter filters out the wideband noise from the input signal. The noise reduction depends on the oversample ratio which defines the effective bandwidth of the digital filter.
PAGE 27
LTC2440 TYPICAL APPLICATIONS 4.5V TO 5.5V 1µF 15 BUSY LTC2440 14 3 fO REF+ REFERENCE VOLTAGE 13 4 0.1V TO VCC SCK REF– 12 5 SDO IN+ ANALOG INPUT RANGE 6 11 –0.5VREF TO 0.5VREF CS IN– 7 VCC SDI 1, 8, 9, 16 10 EXT GND 2 VCC LTC1799 50Ω 5 OUT 1 RSET 0.1µF 3-WIRE SPI INTERFACE NC V+ GND 4 DIV SET 2 3 2440 TA05 Figure 22. Simple External Clock Source 2440fe For more information www.linear.com/LTC2440 Downloaded from Arrow.com.
PAGE 28
LTC2440 PACKAGE DESCRIPTION Please refer to http://www.linear.com/product/LTC2440#packaging for the most recent package drawings. GN Package 16-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641 Rev B) .189 – .196* (4.801 – 4.978) .045 ±.005 16 15 14 13 12 11 10 9 .254 MIN .009 (0.229) REF .150 – .165 .229 – .244 (5.817 – 6.198) .0165 ±.0015 .150 – .157** (3.810 – 3.988) .0250 BSC RECOMMENDED SOLDER PAD LAYOUT 1 .015 ±.004 × 45° (0.38 ±0.10) .007 – .0098 (0.178 – 0.249) .
PAGE 29
LTC2440 REVISION HISTORY (Revision history begins at Rev E) REV DATE DESCRIPTION E 01/17 Updated Max value for fEOSC. PAGE NUMBER 4 Updated formula for tCONV. 4 Updated Note 13. 4 Revised Table 6. Performance vs Oversample Ratio. 25 2440fe Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representaFor more www.linear.
PAGE 30
LTC2440 TYPICAL APPLICATION VREF 100k 3 TOP_P LT1461-5 10µF TOP_N 2 1 VREF +7V 4 5,6,7,8 + 100k 10Ω 2X LT1677 – 4 0.1µF REF+ 0.047µF 1k 0.1% IN+ 1µF LTC2440 100Ω 0.1% 1k 0.1% – VREF 100k 3 1µF 0.047µF REF– 10Ω + 4 2440 F22 BOTTOM_P 2X SILICONIX SI9801 5,6,7,8 BOTTOM_N 2 1 IN– 100k Figure 23. Bridge Reversal Eliminates 1/f Noise and Offset Drift of a Low Noise, Non-Autozeroed, Bipolar Amplifier.