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LTC2442

2442fa

For more information www.linear.com/LTC2442

DIFFERENTIAL (V)

–2.048

–5

ERROR (ppm)

–4

–2

–1

–1.024

2442 TA02

–3

1.024

2.048

INCM

= 2.048V

REF

= 4.096V

= 5V

–

= 0V

24-Bit High Speed

4-Channel DS ADC

with Integrated Amplifier

The LTC

2442 is an ultra high precision, variable speed,

24-bit DS

ADC with integrated amplifier. The amplifier

can be configured as a buffer for easy input drive of high

impedance sensors. 1 part-per-million (ppm) linearity is

achievable when the amplifier is configured in unity gain.

External resistors can be used to set a gain for increased

resolution of low level input signals. The positive and

negative amplifier supply pins may be tied directly to V

(4.5V to 5.5V) and GND or biased above V

and below

GND for rail-to-rail input signals.

The proprietary DS architecture ensures stable DC ac

curacy through continuous transparent calibration. Ten

speed/resolution combinations from 6.9Hz/220nV

RMS

3.5kHz/25µV

RMS

can be selected with no latency or shift

in DC accuracy. Additionally, a 2X speed mode can be

selected enabling output rates up to 7kHz (8kHz with an

external oscillator) with one cycle latency.

Any combination of single-ended (up to 4 inputs) or dif

ferential (up to 2 inputs) can be selected with a common

mode input range from ground to V

. While operating in

the 1X speed mode the

first conversion following a new

speed/resolution or channel selection is valid.

Auto Ranging 6-Digit DVMs

High Speed Multiplexing

Weight Scales

Direct Temperature Measurement

High Speed Data Acquisition

1ppm Linearity with No Missing Codes

Integrated Amplifier for Direct Sensor Digitization

2 Differential or 4 Single-Ended Input Channels

Up to 8kHz Output Rate

Up to 4kHz Multiplexing Rate

Selectable Speed/Resolution

2µV

RMS

Noise at 1.76kHz Output Rate

220nV

RMS

Noise at 13.8Hz Output Rate with

Simultaneous 50Hz/60Hz Rejection

Guaranteed Modulator Stability and Lock-Up

Immunity for any Input and Reference Conditions

<5µV Offset (4.5V < V

< 5.5V, –40°C to 85°C)

Differential Input and Differential Reference with GND

to V

Common Mode Range

No Latency Mode, Each Conversion is Accurate Even

After a New Channel is Selected

Internal Oscillator—No External Components

36-Lead SSOP Package

High Precision Data Acquisition System

LTC2442 Integral Non-Linearity

SDI

SCK

SDO

4.5V TO 5.5V4.5V TO 15V

–15V TO 0V

0.1µF

GND

REF

–

REF

2442 TA01

4-WIRE

SPI INTERFACE

LTC2442

= EXTERNAL OSCILLATOR

= INTERNAL OSCILLATOR

(SIMULTANEOUS 50Hz/60Hz

REJECTION AT 6.9Hz OUTPUT RATE)

CH0

CH1

CH2

CH3

COM

0.1µF

AUTO-CAL

VARIABLE SPEED/

RESOLUTION

DIFFERENTIAL

24-BIT ∆Σ ADC

HIGH Z

2-CHANNEL

DIFFERENTIAL/

4-CHANNEL

SINGLE ENDED

–

Features

applications

description

typical application

L, LT, LT C , LT M, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. No Latency DS and SoftSpan are trademarks of Linear Technology

Corporation. All other trademarks are the property of their respective owners. Protected by U.S.

Patents including 6140950, 6169506, 6411242, 6639526.

Summary of content (32 pages)

PAGE 1
LTC2442 24-Bit High Speed 4-Channel DS ADC with Integrated Amplifier description Features 1ppm Linearity with No Missing Codes n Integrated Amplifier for Direct Sensor Digitization n 2 Differential or 4 Single-Ended Input Channels n Up to 8kHz Output Rate n Up to 4kHz Multiplexing Rate n Selectable Speed/Resolution 2µV RMS Noise at 1.76kHz Output Rate 220nV RMS Noise at 13.
PAGE 2
LTC2442 Absolute Maximum Ratings Pin Configuration (Notes 1, 2) TOP VIEW Supply Voltage (VCC) to GND........................ –0.3V to 6V Analog Input Pins Voltage to GND.......................................–0.3V to (VCC + 0.3V) Reference Input Pins Voltage to GND.......................................–0.3V to (VCC + 0.3V) Digital Input Voltage to GND..........–0.3V to (VCC + 0.3V) Digital Output Voltage to GND........–0.3V to (VCC + 0.3V) Operating Temperature Range LTC2442CG...........................
PAGE 3
LTC2442 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4, 15) PARAMETER CONDITIONS MIN TYP MAX UNITS l l 2 2 1 10 7 ppm of VREF ppm of VREF ppm of VREF l 2.5 5 µV Resolution (No Missing Codes) 0.1V ≤ VREF ≤ VCC, –0.5 • VREF ≤ VIN ≤ 0.5 • VREF (Note 5) Integral Nonlinearity VCC = 5V, REF+ = 5V, REF– = GND, VINCM = 2.5V (Note 6, 14) VCC = 5V, REF+ = 2.
PAGE 4
LTC2442 digital inputs and digital outputs The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) SYMBOL PARAMETER CONDITIONS VIH High Level Input Voltage CS, FO, EXT, SDI 4.5V ≤ VCC ≤ 5.5V l MIN VIL Low Level Input Voltage CS, FO, EXT, SDI 4.5V ≤ VCC ≤ 5.5V l VIH High Level Input Voltage SCK 4.5V ≤ VCC ≤ 5.5V (Note 8) l VIL Low Level Input Voltage SCK 4.5V ≤ VCC ≤ 5.
PAGE 5
LTC2442 timing Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX fEOSC External Oscillator Frequency Range l 0.1 20 UNITS MHz tHEO External Oscillator High Period l 25 10000 ns tLEO External Oscillator Low Period l 25 10000 ns tCONV Conversion Time OSR = 256 (SDI = 0) OSR = 32768 (SDI = 1) l l 0.99 126 1.
PAGE 6
LTC2442 typical performance Characteristics Integral Non-Linearity vs Temperature 5 6 1 0 –1 –2 –40°C 4 2 –4 0 –2 25°C –4 90°C –0.75 0.25 0.75 –0.25 INPUT VOLTAGE (V) 0 V+ = 5.5V –6 –8 0.5 –0.5 VIN (V) 2 0 V– = –2V –2 V– = –1V –4 V– = 0V –6 1.5 –10 –2.5 2.5 –1.5 0.5 –0.5 VIN (V) 1.5 –2.5 1000 1500 2000 2500 3000 3500 CONVERSION RATE (Hz) 2442 G07 –5.0 4.5 2.5 4.7 5.1 4.9 VCC (V) 5.3 SEL+ = SEL– = V VCC = 5V OSR = 32768 VREF = 5V VREF+ = 5V FO = GND – = GND TA = 25°C 2.
PAGE 7
LTC2442 pin functions SCK (Pin 1): Bidirectional Digital Clock Pin. In internal serial clock operation mode, SCK is used as a digital output for the internal serial interface clock during the data output period. In the external serial clock operation mode, SCK is used as the digital input for the external serial interface clock during the data output period. The serial clock operation mode is determined by the logic level applied to EXT (Pin 3). BUSY (Pin 2): Conversion in Progress Indicator.
PAGE 8
LTC2442 pin functions VCC (Pin 29): Positive Supply Voltage. Bypass to GND with a 10µF tantalum capacitor in parallel with a 0.1µF ceramic capacitor as close to the part as possible. REF+ (Pin 30), REF– (Pin 31): Differential Reference Input. The voltage on these pins can have any value between GND and VCC as long as the reference positive input, REF+, is maintained more positive than the negative reference input, REF–, by at least 0.1V. Bypass to GND with 0.
PAGE 9
LTC2442 test circuits VCC 1.69k SDO SDO 1.69k Hi-Z TO VOH VOL TO VOH VOH TO Hi-Z CLOAD = 20pF CLOAD = 20pF Hi-Z TO VOL VOH TO VOL VOL TO Hi-Z 2442 TA03 2442 TA04 Applications Information CONVERTER OPERATION POWER UP IN+=CH0, IN–=CH1 OSR=256,1X MODE Converter Operation Cycle The LTC2442 is a multi-channel, high speed, DS analog-to-digital converter with an easy to use 3- or 4-wire serial interface (see Figure 1). Its operation is made up of three states.
PAGE 10
LTC2442 Applications Information sult is shifted out on the serial data out pin (SDO) under the control of the serial clock (SCK). Data is updated on the falling edge of SCK allowing the user to reliably latch data on the rising edge of SCK (see Figure 3). The data output state is concluded once 32 bits are read out of the ADC or when CS is brought HIGH. In either scenario, the device automatically initiates a new conversion and the cycle repeats.
PAGE 11
LTC2442 Applications Information Reference Voltage Range The LTC2442 DS converter accepts a truly differential external reference voltage. The absolute/common mode voltage specification for the REF+ and REF– pins covers the entire range from GND to VCC. For correct converter operation, the REF+ pin must always be more positive than the REF– pin. The LTC2442 can accept a differential reference voltage from 0.1V to VCC.
PAGE 12
LTC2442 Applications Information Serial Clock Input/Output (SCK) the first falling edge of SCK. The final data bit (Bit 0) is shifted out on the falling edge of the 31st SCK and may be latched on the rising edge of the 32nd SCK pulse. On the falling edge of the 32nd SCK pulse, SDO goes HIGH indicating the initiation of a new conversion cycle. This bit serves as EOC (Bit 31) for the next conversion cycle. Table 2 summarizes the output data format.
PAGE 13
LTC2442 Applications Information Table 3. Channel Selection MUX ADDRESS CHANNEL SELECTION SGL ODD/SIGN A2 A1 A0 CH0 CH1 0 0 0 0 0 SEL+ SEL– 0 0 0 0 1 0 1 0 0 0 0 1 0 0 1 1 0 0 0 0 1 0 0 0 1 1 1 0 0 0 1 1 0 0 1 SEL– CH2 CH3 SEL+ SEL– SEL– SEL+ COM SEL+ SEL+ SEL– SEL+ SEL– SEL+ SEL– SEL+ SEL– Table 4. Speed/Resolution Selection OSR3 OSR2 OSR1 OSR0 TWOX CONVERSION RATE INTERNAL 9MHZ Clock EXTERNAL 10.
PAGE 14
LTC2442 Applications Information Chip Select Input (CS) The active LOW chip select, CS (Pin 35), is used to test the conversion status and to enable the data output transfer as described in the previous sections. In addition, the CS signal can be used to trigger a new conversion cycle before the entire serial data transfer has been completed.
PAGE 15
LTC2442 Applications Information selected speed/resolution and input channel is valid. This is identical to the operation of the LTC2440 and LTC2444 through LTC2449. While operating in the 2X mode, the device performs a running average of the last two conversion results. This automatically removes the offset and drift of the device while increasing the output rate by 2X. The resolution (noise) remains the same.
PAGE 16
LTC2442 Applications Information External Serial Clock, Single Cycle Operation (SPI/MICROWIRE Compatible) When the device is in the sleep state (EOC = 0), its conversion result is held in an internal static shift register. The device remains in the sleep state until the first rising edge of SCK is seen. Data is shifted out the SDO pin on each falling edge of SCK. This enables external circuitry to latch the output on the rising edge of SCK.
PAGE 17
LTC2442 Applications Information As described above, CS may be pulled LOW at any time in order to monitor the conversion status on the SDO pin. is aborted prior to the 13th rising edge of SCK, the new input data is ignored, and the previously selected speed/ resolution and channel are used for the next conversion cycle. This is useful for systems not requiring all 32 bits of output data, aborting an invalid conversion cycle or synchronizing the start of a conversion.
PAGE 18
LTC2442 Applications Information External Serial Clock, 2-Wire I/O controller indicating the conversion result is ready. EOC = 1 (BUSY = 1) while the conversion is in progress and EOC = 0 (BUSY = 0) once the conversion enters the sleep state. On the falling edge of EOC/BUSY, the conversion result is loaded into an internal static shift register. The device remains in the sleep state until the first rising edge of SCK.
PAGE 19
LTC2442 Applications Information Internal Serial Clock, Single Cycle Operation conversion and goes LOW at the conclusion. It remains LOW until the result is read from the device. This timing mode uses an internal serial clock to shift out the conversion result and a CS signal to monitor and control the state of the conversion cycle, see Figure 7. When testing EOC, if the conversion is complete (EOC = 0), the device will exit the sleep state and enter the data output state if CS remains LOW.
PAGE 20
LTC2442 Applications Information If CS remains LOW longer than tEOCtest, the first rising edge of SCK will occur and the conversion result is serially shifted out of the SDO pin. The data output cycle begins on this first rising edge of SCK and concludes after the 32nd rising edge. Data is shifted out the SDO pin on each falling edge of SCK. The internally generated serial clock is output to the SCK pin. This signal may be used to shift the conversion result into external circuitry.
PAGE 21
LTC2442 Applications Information device has entered the sleep state. The part remains in the sleep state a minimum amount of time (≈500ns) then immediately begins outputting data. The data output cycle begins on the first rising edge of SCK and ends after the 32nd rising edge. Data is shifted out the SDO pin on each falling edge of SCK. The internally generated serial clock is output to the SCK pin. This signal may be used to shift the conversion result into external circuitry.
PAGE 22
LTC2442 Applications Information Normal Mode Rejection and Antialiasing One of the advantages delta-sigma ADCs offer over conventional ADCs is on-chip digital filtering. Combined with a large oversampling ratio, the LTC2442 significantly simplifies antialiasing filter requirements. The LTC2442’s speed/resolution is determined by the oversample ratio (OSR) of the on-chip digital filter. The OSR ranges from 64 for 3.5kHz output rate to 32,768 for 6.9Hz (in No Latency mode) output rate.
PAGE 23
LTC2442 Applications Information If FO is grounded, fS is set by the on-chip oscillator at 1.8MHz ±5% (over supply and temperature variations). At an OSR of 32,768, the first NULL is at fN = 55Hz and the no latency output rate is fN/8 = 6.9Hz. At the maximum OSR, the noise performance of the device is 220nVRMS with better than 80dB rejection of 50Hz ±2% and 60Hz ±2%. Since the OSR is large (32,768) the wide band rejection is extremely large and the antialiasing requirements are simple.
PAGE 24
LTC2442 Applications Information Input Bandwidth and Frequency Rejection First Notch Frequency The combined effect of the internal SINC4 digital filter and the digital and analog autocalibration circuits determines the LTC2442 input bandwidth and rejection characteristics. The digital filter’s response can be adjusted by setting the oversample ratio (OSR) through the SPI interface or by supplying an external conversion clock to the fO pin.
PAGE 25
LTC2442 Applications Information Optimizing Linearity While the integrated op-amp has rail-to-rail input range, in order to achieve parts-per-million linearity performance, the input range and op-amp supply voltages must be considered. Input levels within 1.25V of the upper op-amp rail (V+) begin to degrade the performance. For example (see Figure 15) while operating with V+ = 5.1V and absolute input voltages (VINCM + VINDIFF) up to 3.75V (VINCM = 2.5V and –2.5V < VINDIFF < 2.
PAGE 26
LTC2442 Applications Information Input Bias Current The LTC2442 breaks new ground in high impedance input DS ADCs. The input buffer is optimized to make driving the ADC as easy as possible, while overcoming many of the limitations typical of integrated buffers. The 10nA typical bias current of the buffers results in less than 1ppm (5µV) error for source resistance imbalances of less than 500W. Matching the resistance at the inputs cancels much of the error due to amplifier bias current.
PAGE 27
LTC2442 Applications Information Low Power Operation The integrated buffers have a supply current of 1mA total, greatly reducing the total power consumption when the ADC is operated at a low duty cycle. The typical approach to driving a DS ADC is to use a high bandwidth amplifier that settles very quickly in response to the sampling process at the ADC input. The LTC2442 approach is to use an accurate, low bandwidth amplifier that requires a load capacitor for compensation.
PAGE 28
LTC2442 Applications Information VIN1 5V 2 IN OUT LT1236N U3 GND TRIM REF+ 6 4.7µF C15 5 1Ω R20 4 R1 40k 5V 3 4 + 6 1 U2 – REF+ 30 –2.5V REF+ 31 REF– 6 R5 8.88k 7 8 5 2 9 LTC2050HV –5V 28 10 11 VIN2 30k R6 R9 10k 2.5V 5V 29 5k R4 5k R3 0.1µF C13 –2.5V R10 7.5k C14 0.1µF C10 0.1µF 12 13 17 18 21 V+ VCC CS LTC2442 U1 CH0 SCK SD0 CH1 SDI CH2 BUSY CH3 FO COM EXT ADCINB MUOUTA ADCINA MUXOUTB 35 1 36 33 2 34 3 –2.
PAGE 29
LTC2442 Applications Information Details of the Conversion and Autozero Process The LTC2442 performs automatic offset cancellation for each conversion. This is accomplished by taking the average of two “half-conversions” with the inputs applied in opposite polarity. Figure 21 shows a conversion on CH0 to CH1 differential at OSR of 32768, in 1x mode. This channel is selected by sending the appropriate configuration word to the LTC2442 through the SPI interface.
PAGE 30
LTC2442 package description G Package 36-Lead Plastic SSOP (5.3mm) (Reference LTC DWG # 05-08-1640) 12.50 – 13.10* (.492 – .516) 1.25 ±0.12 7.8 – 8.2 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 5.3 – 5.7 0.42 ±0.03 7.40 – 8.20 (.291 – .323) 0.65 BSC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 RECOMMENDED SOLDER PAD LAYOUT 2.0 (.079) MAX 5.00 – 5.60** (.197 – .221) 0° – 8° 0.09 – 0.25 (.0035 – .010) 0.65 (.0256) BSC 0.55 – 0.95 (.022 – .037) NOTE: 1.
PAGE 31
LTC2442 Revision History REV DATE DESCRIPTION A 06/13 Corrected the resistor and capacitor units on R20, C15, C13, C8, C14, C10, C17, C9 in the Typical Application circuit PAGE NUMBER 28, 32 2442fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection its circuits as described herein will not infringe on existing patent rights.
PAGE 32
LTC2442 typical application Scaling Inputs for ±10V Range VIN1 5V 2 IN OUT LT1236N U3 GND TRIM REF+ 6 4.7µF C15 5 1Ω R20 4 R1 40k 5V 3 4 + 6 30 –2.5V REF+ 31 REF– 6 R5 8.88k 1 U2 – REF+ 7 8 5 2 9 LTC2050HV –5V 28 10 11 VIN2 30k R6 2.5V 5V 29 5k R4 5k R3 0.1µF C13 –2.5V R9 10k R10 7.5k C14 0.1µF 12 C10 0.1µF 13 17 18 21 V+ VCC CS LTC2442 U1 CH0 0.1µF C8 SCK SD0 CH1 SDI CH2 BUSY CH3 FO COM EXT ADCINB MUOUTA ADCINA MUXOUTB 35 1 36 33 2 34 3 –2.