Datasheet

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LTC2452

2452fd

For more information www.linear.com/LTC2452

Typical applicaTion

FeaTures

applicaTions

DescripTion

Ultra-Tiny, Differential, 16-Bit

∆

Σ ADC with SPI Interface

The LT C

2452 is an ultra-tiny, fully differential, 16-bit,

analog-to-digital converter. The LTC2452 uses a single

2.7V to 5.5V supply and communicates through an SPI

interface. The ADC is available in an 8-pin, 3mm

2mm

DFN package or TSOT-23 package. It includes an integrated

oscillator that does not require any external components.

It uses a delta-sigma modulator as a converter core and

has no latency for multiplexed applications. The LTC2452

includes a proprietary input sampling scheme that reduces

the average input sampling current several orders of

magnitude when compared to conventional delta-sigma

converters. Additionally, due to its architecture, there is

negligible current leakage between the input pins.

The LTC2452 can sample at 60 conversions per second,

and due to the very large oversampling ratio, has extremely

relaxed anti-aliasing requirements. The LTC2452 includes

continuous internal offset and full-scale calibration algo

rithms which are

transparent to the user, ensuring accuracy

over time and over the operating temperature range. The

converter has an external REF pin and the differential input

voltage range can extend up to ±V

REF

Following a single conversion, the LTC2452 can automati-

cally

enter a sleep mode and reduce its supply current to

less

than 0.2µA. If the user reads the ADC once a second,

the LTC2452 consumes an average of less than 50µW

from a 2.7V supply.

Integral Nonlinearity, V

= 3V

±V

Differential Input Range

16-Bit Resolution (Including Sign), No Missing

Codes

2LSB Offset Error

4LSB Full-Scale Error

60 Conversions Per Second

Single Conversion Settling Time for Multiplexed

Applications

Single-Cycle Operation with Auto Shutdown

800µA Supply Current

0.2µA Sleep Current

Internal Oscillator—No External Components

Required

SPI Interface

Ultra-Tiny 3mm × 2mm DFN and TSOT-23 Packages

System Monitoring

Environmental Monitoring

Direct Temperature Measurements

Instrumentation

Industrial Process Control

Data Acquisition

Embedded ADC Upgrades

L, LT , LT C , LT M, Linear Technology and the Linear logo are registered trademarks and No

Latency ∆Σ is a trademark of Linear Technology Corporation. All other trademarks are the

property of their respective owners. Protected by U.S. Patents, including 6208279, 6411242,

7088280, 7164378.

DIFFERENTIAL INPUT VOLTAGE (V)

–3

INL (LSB)

2452 TA01b

–1

–2

–3

–1–2

1 2

= –45°C, 25°C, 90°C

10k

3-WIRE SPI

INTERFACE

SCK

SDO

0.1µF

0.1µF 10µF

2.7V TO 5.5V

0.1µF

REF V

GND

–

LTC2452

2452 TA01a

Summary of content (22 pages)

PAGE 1
LTC2452 Ultra-Tiny, Differential, 16-Bit ∆Σ ADC with SPI Interface Description Features n n n n n n n n n n n n ±VCC Differential Input Range 16-Bit Resolution (Including Sign), No Missing Codes 2LSB Offset Error 4LSB Full-Scale Error 60 Conversions Per Second Single Conversion Settling Time for Multiplexed Applications Single-Cycle Operation with Auto Shutdown 800µA Supply Current 0.
PAGE 2
LTC2452 Absolute Maximum Ratings (Notes 1, 2) Supply Voltage (VCC).................................... –0.3V to 6V Analog Input Voltage (VIN+, VIN –)..–0.3V to (VCC + 0.3V) Reference Voltage (VREF)...............–0.3V to (VCC + 0.3V) Digital Voltage (VSDO, VSCK, VCS)..–0.3V to (VCC + 0.3V) Storage Temperature Range................... –65°C to 150°C Operating Temperature Range LTC2452C................................................. 0°C to 70°C LTC2452I..............................................
PAGE 3
LTC2452 Analog Inputs And References The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 0 VREF V l 0 VREF V l 2.5 + Positive Input Voltage Range l VIN – Negative Input Voltage Range VREF Reference Voltage Range VOR+ + VUR+ Overrange + Underrange Voltage, IN+ VREF = 5V, VIN– = 2.
PAGE 4
LTC2452 Timing Characteristics The l denotes the specifications which apply over the full operating temperature range,otherwise specifications are at TA = 25°C.
PAGE 5
LTC2452 Typical Performance Characteristics Gain Error vs Temperature 5 4 4 3 3 2 2 1 VCC = VREF = 5V 0 –1 –2 VCC = VREF = 3V –3 VCC = VREF = 4.1V Transition Noise vs Temperature 10 9 VCC = VREF = 3V TRANSITION NOISE RMS (µV) 5 GAIN ERROR (LSB) OFFSET ERROR (LSB) Offset Error vs Temperature (TA = 25°C, unless otherwise noted) VCC = VREF = 4.1V 1 0 VCC = VREF = 5V –1 –2 –3 –4 –4 –5 –50 –25 25 50 0 TEMPERATURE (°C) 75 –25 25 50 0 TEMPERATURE (°C) 75 2452 G04 VCC = 4.
PAGE 6
LTC2452 Pin Functions SCK (Pin 1): Serial Clock Input. SCK synchronizes the serial data output. While digital data is available (the ADC is not in CONVERT state) and CS is LOW (ADC is not in SLEEP state) a new data bit is produced at the SDO output pin following every falling edge applied to the SCK pin. GND (Pin 2): Ground. Connect to a ground plane through a low impedance connection. REF (Pin 3): Reference Input. The voltage on REF can have any value between 2.5V and VCC.
PAGE 7
LTC2452 applications information of data appears at the SDO pin following each falling edge detected at the SCK input pin and appears from MSB to LSB. The user can reliably latch this data on every rising edge of the external serial clock signal driving the SCK pin (see Figure 3). POWER-ON RESET CONVERT SLEEP NO The DATA OUTPUT state concludes in one of two different ways. First, the DATA OUTPUT state operation is completed once all 16 data bits have been shifted out and the clock then goes low.
PAGE 8
LTC2452 applications information of magnitude when compared to traditional delta-sigma architectures. This allows external filter networks to interface directly to the LTC2452. Since the average input sampling current is 50nA, an external RC lowpass filter using 1kΩ and 0.1µF results in <1LSB additional error. Additionally, there is negligible leakage current between IN+ and IN–. 20 16 12 OUTPUT CODE 8 4 0 –4 SIGNALS BELOW GND –8 –12 –16 Reference Voltage Range –20 –0.
PAGE 9
LTC2452 Applications Information t1 t3 t2 CS D14 D15 SDO D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 MSB D0 LSB SCK 2452 F04 tKQ tlSCK thSCK Figure 4. Data Output Timing t2 t1 CS SDO SCK = HIGH CONVERT SLEEP 2452 F05 Figure 5. Conversion Status Monitoring Mode with the most significant bit of the result being present at the SDO output pin (SDO = D15) once CS goes low. A new data bit appears at the SDO output pin after each falling edge detected at the SCK input pin.
PAGE 10
LTC2452 applications information 2) After the 16th bit is read, the user can choose one of two ways to begin a new conversion. First, one can pull CS high (CS = ↑). Second, one can use a high-low transition on SCK (SCK = ↓). Pulling CS LOW while SCK is HIGH tests whether or not the chip is in the CONVERT state. While in the CONVERT state, SDO is HIGH while CS is LOW. In the SLEEP state, SDO is LOW while CS is LOW. These tests are not required operational steps but may be useful for some applications.
PAGE 11
LTC2452 Applications Information CS SD0 D15 D14 D13 clk1 clk2 clk3 D12 D2 D1 D0 clk15 clk16 SCK CONVERT SLEEP clk4 clk14 DATA OUTPUT CONVERT 2452 F08 Figure 8. Idle-Low (CPOL = 0) Clock. CS Triggers a New Conversion CS SD0 D15 D14 clk1 clk2 D13 D12 D2 D1 clk14 clk15 D0 SCK CONVERT SLEEP clk3 clk4 DATA OUTPUT clk16 CONVERT 2452 F09 Figure 9. Idle-Low (CPOL = 0) Clock. The 16th SCK Falling Edge Triggers a New Conversion based upon external timing.
PAGE 12
LTC2452 applications information CS SD0 D15 D14 D13 SCK clk1 CONVERT SLEEP clk2 clk3 clk4 DATA OUTPUT CONVERT 2452 F10 Figure 10. Idle-High (CPOL = 1) Clock and Aborted I/O Example CS SD0 D15 D14 clk1 clk2 D13 SCK CONVERT SLEEP clk3 DATA OUTPUT CONVERT 2452 F11 Figure 11. Idle-Low (CPOL = 0) Clock and Aborted I/O Example CS SD0 D15 SCK = LOW CONVERT SLEEP DATA OUTPUT CONVERT 2452 F12 Figure 12.
PAGE 13
LTC2452 Applications Information status can be monitored at the SDO output. Following a conversion cycle, the ADC enters SLEEP state and the SDO output transitions from HIGH to LOW. Subsequently 16 clock pulses are applied to the SCK input in order to serially shift the 16 bit result. Finally, the 17th clock pulse is applied to the SCK input in order to trigger a new conversion cycle.
PAGE 14
LTC2452 applications information PRESERVING THE CONVERTER ACCURACY The LTC2452 is designed to minimize the conversion result’s sensitivity to device decoupling, PCB layout, anti-aliasing circuits, line and frequency perturbations. Nevertheless, in order to preserve the high accuracy capability of this part, some simple precautions are desirable. Digital Signal Levels Due to the nature of CMOS logic, it is advisable to keep input digital signals near GND or VCC. Voltages in the range of 0.5V to VCC – 0.
PAGE 15
LTC2452 Applications Information A 0.1µF, high quality, ceramic capacitor in parallel with a 10µF ceramic capacitor should be connected between the REF and GND pins, as close as possible to the package. The 0.1µF capacitor should be placed closest to the ADC. 2) The bandwidth from VSIG is reduced at the input pins (IN+, IN–). This bandwidth reduction isolates the ADC from high frequency signals, and as such provides simple anti-aliasing and input noise reduction.
PAGE 16
LTC2452 applications information In the case of a 2-wire sensor that is not remotely grounded, it is desirable to split RS and place series resistors in the ADC input line as well as in the sensor ground return line, which should be tied to the ADC GND pin using a star connection topology. Figure 17 shows the measured LTC2452 INL vs Input Voltage as a function of RS value with an input capacitor CIN = 0.1µF. In some cases, RS can be increased above these guidelines.
PAGE 17
LTC2452 Applications Information Signal Bandwidth, Transition Noise and Noise Equivalent Input Bandwidth The LTC2452 includes a SINC1 type digital filter with the first notch located at f0 = 60Hz. As such, the 3dB input signal bandwidth is 26.54Hz. The calculated LTC2452 input signal attenuation vs frequency over a wide frequency range is shown in Figure 19. The calculated LTC2452 input signal attenuation vs frequency at low frequencies is shown in Figure 20. The converter noise level is about 2.
PAGE 18
LTC2452 typical application JP1 VCC VCC U2 3 LT6660HCDC-5 1 IN OUT V+ 1µF GND GND 2 +5V EXT 1 2 3 1µF GND 4 1k REF+ VCC 0.1µF 0.1µF 3 IN+ IN– 1k 1k 0.1µF 0.1µF 6 IN+ 5 IN– 0.1µF CS SCK SDO 4 REF+ VCC LTC2452 REF– GND 2 1µF CS SCK SDO 7 U1* 1 8 9 VCC V+ 1 10V 2 5V TO CONTROLLER 6 CS 4 SCK/SCL 7 MOSI/SDA 5 MISO/SDO GND GND GND 3 8 13 2452 TA02 18 2452fd For more information www.linear.
PAGE 19
LTC2452 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. DDB Package 8-Lead Plastic DFN (3mm × 2mm) (Reference LTC DWG # 05-08-1702 Rev B) 0.61 ±0.05 (2 SIDES) 0.70 ±0.05 2.55 ±0.05 1.15 ±0.05 PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 2.20 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 3.00 ±0.10 (2 SIDES) R = 0.115 TYP 5 R = 0.05 TYP 0.40 ± 0.10 8 2.00 ±0.10 (2 SIDES) PIN 1 BAR TOP MARK (SEE NOTE 6) 0.56 ± 0.
PAGE 20
LTC2452 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. TS8 Package 8-Lead Plastic TSOT-23 (Reference LTC DWG # 05-08-1637 Rev A) 0.40 MAX 2.90 BSC (NOTE 4) 0.65 REF 1.22 REF 1.4 MIN 3.85 MAX 2.62 REF 2.80 BSC 1.50 – 1.75 (NOTE 4) PIN ONE ID RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR 0.22 – 0.36 8 PLCS (NOTE 3) 0.65 BSC 0.80 – 0.90 0.20 BSC 0.01 – 0.10 1.00 MAX DATUM ‘A’ 0.30 – 0.50 REF 0.09 – 0.20 (NOTE 3) 1.
PAGE 21
LTC2452 Revision History (Revision history begins at Rev C) REV DATE DESCRIPTION PAGE NUMBER C 03/10 Updated Analog Inputs and References section D 03/14 3 Added text to Input Voltage Range section 8 Changed VIN+ and VIN– Input Voltage Range (MAX) to VREF 3 2452fd Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use.
PAGE 22
LTC2452 related parts PART NUMBER DESCRIPTION COMMENTS LT1236A-5 Precision Bandgap Reference, 5V 0.05% Max, 5ppm/°C Drift LT1461 Micropower Series Reference, 2.5V 0.04% Max, 3ppm/°C Drift LT1790 Micropower Precision Reference in TSOT-23-6 Package 60µA Max Supply Current, 10ppm/°C Max Drift, 1.25V, 2.048V, 2.5V, 3V, 3.3V, 4.096V and 5V Options LTC2440 24-Bit No Latency ∆S™ ADC 200nVRMS Noise, 4kHz Output Rate, 15ppm INL LTC2480 16-Bit, Differential Input, No Latency ∆S ADC, with PGA, Temp.