Datasheet

ManualsBrandsLINEAR TECHNOLOGY ManualsData collecting ICsData acquisition IC - AD converter (ADC) Internal DFN 12

LTC2461/LTC2463

24613fa

–50 –10 10–30 50 7030 90

TEMPERATURE (°C)

REFERENCE OUTPUT VOLTAGE (V)

1.2520

1.2515

1.2510

1.2505

1.2500

24613 TA01b

1.2480

1.2485

1.2490

1.2495

TYPICAL APPLICATION

FEATURES

APPLICATIONS

DESCRIPTION

Ultra-Tiny, 16-Bit I

C ΔΣ

ADCs with 10ppm/°C Max

Precision Reference

The LTC

2461/LTC2463 are ultra tiny, 16-Bit analog-to-

digital converters with an integrated precision reference.

They use a single 2.7V to 5.5V supply and communicate

through an I

C Interface. The LTC2461 is single-ended

with a 0V to 1.25V input range and the LTC2463 is dif-

ferential with a 1.25V input range. Both ADCs include a

1.25V integrated reference with 2ppm/°C drift perfor-

mance and 0.1% initial accuracy. The converters are

available in a 12-pin 3mm × 3mm DFN package or an

MSOP-12 package. They include an integrated oscillator

and perform conversions with no latency for multiplexed

applications. The LTC2461/LTC2463 include a proprietary

input sampling scheme that reduces the average input

current several orders of magnitude when compared to

conventional delta sigma converters.

Following a single conversion, the LTC2461/LTC2463

automatically power down the converter and can also be

conﬁgured to power down the reference. When both the

ADC and reference are powered down, the supply current

is reduced to 200nA.

The LTC2461/LTC2463 can sample at 60 conversions per

second and, due to the very large oversampling ratio,

have extremely relaxed antialiasing requirements. Both

include continuous internal offset and fullscale calibration

algorithms which are transparent to the user, ensuring ac-

curacy over time and the operating temperature range.

REF

vs Temperature

16-Bit Resolution, No Missing Codes

Internal Reference, High Accuracy 10ppm/°C (Max)

Single-Ended (LTC2461) or Differential (LTC2463)

2LSB Offset Error (Typ)

0.01% Gain Error (Typ)

60 Conversions Per Second

Single Conversion Settling Time for Multiplexed

Applications

1.5mA Supply Current

200nA Sleep Current

Internal Oscillator—No External Components

Required

2-Wire I

C Interface with Two Addresses Plus One

Global Address for Synchronization

Ultra-Tiny, 12-Lead, 3mm × 3mm DFN and MSOP

Packages

System Monitoring

Environmental Monitoring

Direct Temperature Measurements

Instrumentation

Data Acquisition

Embedded ADC Upgrades

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

Protected by U.S. Patents, including 6208279, 6411242, 7088280, 7164378.

10k

SCL

INTERFACE

SDA

0.1µF

2.7V TO 5.5V

10µF

0.1µF

REFOUT

REF

–

0.1µF

COMP

GND

–

0.1µF

LTC2463

24613 TA01a

Summary of content (20 pages)

PAGE 1
LTC2461/LTC2463 Ultra-Tiny, 16-Bit I2C ΔΣ ADCs with 10ppm/°C Max Precision Reference DESCRIPTION FEATURES n n n n n n n n n n n n 16-Bit Resolution, No Missing Codes Internal Reference, High Accuracy 10ppm/°C (Max) Single-Ended (LTC2461) or Differential (LTC2463) 2LSB Offset Error (Typ) 0.01% Gain Error (Typ) 60 Conversions Per Second Single Conversion Settling Time for Multiplexed Applications 1.
PAGE 2
LTC2461/LTC2463 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) Supply Voltage (VCC).................................... –0.3V to 6V Analog Input Voltage (VIN+, VIN –, VIN, VREF –, VCOMP, VREFOUT )............................–0.3V to (VCC + 0.3V) Digital Voltage (VSDA, VSCL, VA0)...........................–0.3V to (VCC + 0.3V) Storage Temperature Range................... –65°C to 150°C Operating Temperature Range LTC2461C/LTC2463C................................ 0°C to 70°C LTC2461I/LTC2463I........................
PAGE 3
LTC2461/LTC2463 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 2) PARAMETER CONDITIONS MIN TYP MAX UNITS 16 Bits Resolution (No Missing Codes) (Note 3) l Integral Nonlinearity (Note 4) l 1 8 LSB Offset Error LTC2461, 30Hz, LTC2463 LTC2461, 60Hz l 2 5 15 LSB LSB Offset Error Drift 0.02 LSB/°C Gain Error Includes Contributions of ADC and Internal Reference l ±0.
PAGE 4
LTC2461/LTC2463 I2C INPUTS AND OUTPUTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 2, 7) SYMBOL PARAMETER VIH High Level Input Voltage CONDITIONS l MIN VIL Low Level Input Voltage l II Digital Input Current l –10 0.05VCC TYP MAX UNITS 0.7VCC V 0.3VCC V 10 µA VHYS Hysteresis of Schmidt Trigger Inputs (Note 3) l VOL Low Level Output Voltage (SDA) I = 3mA l 0.
PAGE 5
LTC2461/LTC2463 TYPICAL PERFORMANCE CHARACTERISTICS Integral Nonlinearity (VCC = 5.5V) Integral Nonlinearity (VCC = 2.7V) 3 TA = –45°C, 25°C, 90°C TA = –45°C, 25°C, 90°C 2 1 1 1 0 INL (LSB) 2 0 –1 –1 –2 –2 –2 0.25 0.75 –0.75 –0.25 DIFFERENTIAL INPUT VOLTAGE (V) –3 –1.25 1.25 0.25 0.75 –0.75 –0.25 DIFFERENTIAL INPUT VOLTAGE (V) 24613 G01 Offset Error vs Temperature ADC Gain Error vs Temperature Transition Noise vs Temperature 10 ADC GAIN ERROR (LSB) VCC = 4.1V 1 VCC = 2.
PAGE 6
LTC2461/LTC2463 TYPICAL PERFORMANCE CHARACTERISTICS CONVERSION TIME (ms) –20 REJECTION (dB) Conversion Time vs Temperature TA = 25°C VCC = 4.1V –40 –60 –80 –100 –120 21 1.24892 20 1.24891 VCC = 5V, 4.1V, 3V 18 17 10 100 1k 10k 100k FREQUENCY AT VCC (Hz) 1M 14 –50 10M 24613 G10 TA = 25°C 1.24889 1.24888 1.24887 16 1.24886 15 1 VREF vs VCC 1.24890 19 VREF (V) 0 Power Supply Rejection vs Frequency at VCC (TA = 25°C, unless otherwise noted) 1.
PAGE 7
LTC2461/LTC2463 BLOCK DIAGRAM 1 9 10 IN+ (IN) IN– (GND) 2 REFOUT COMP INTERNAL REFERENCE ∆Σ A/D CONVERTER 12 VCC A0 I2C INTERFACE SCL SDA DECIMATING SINC FILTER – 3 5 6 ∆Σ A/D CONVERTER INTERNAL OSCILLATOR 8 REF– 4, 7, 11, 13 (DD PACKAGE) GND 24613 BD ( ) PARENTHESIS INDICATE LTC2461 Figure 1.
PAGE 8
LTC2461/LTC2463 APPLICATIONS INFORMATION current by approximately 50%. While in the Nap state, the reference remains powered up. To power down the reference in addition to the converter, the user can select the SLEEP mode during the DATA INPUT/OUTPUT state. Once the next conversion is complete, SLEEP state is entered and power is reduced to 200nA. The reference is powered up once a valid read/write is acknowledged.
PAGE 9
LTC2461/LTC2463 APPLICATIONS INFORMATION VREF and below GND, if the differential input is within ±VREF. As an example (Figure 3), if the user desires to measure a signal slightly below ground, the user could set VIN– = GND. If VIN+ = GND, the output code would be approximately 32768. If VIN+ = GND – 8LSB = –0.305mV, the output code would be approximately 32760. For applications that require an input range greater than ±1.25V, please refer to the LTC2453.
PAGE 10
LTC2461/LTC2463 APPLICATIONS INFORMATION The START and STOP Conditions Output Data Format A START (S) condition is generated by transitioning SDA from HIGH to LOW while SCL is HIGH. The bus is considered to be busy after the START condition. When the data transfer is finished, a STOP (P) condition is generated by transitioning SDA from LOW to HIGH while SCL is HIGH. The bus is free after a STOP is generated. START and STOP conditions are always generated by the master.
PAGE 11
LTC2461/LTC2463 APPLICATIONS INFORMATION Data Input Format LTC2463 data output rate is always 60Hz and background offset calibration is performed (SPD = don’t care). After a START condition, the master sends a 7-bit address followed by a read/write request (R/W) bit. The R/W bit is 0 for a write. The data input word is 4 bits long and consists of two enable bits (EN1 and EN2) and two programming bits (SPD and SLP), see Figure 5b.
PAGE 12
LTC2461/LTC2463 APPLICATIONS INFORMATION OPERATION SEQUENCE Discarding a Conversion Result and Initiating a New Conversion Continuous Read It is possible to start a new conversion without reading the old result, as shown in Figure 7b. Following a valid 7-bit address, a read request (R/W) bit, and a valid ACK, a STOP command will start a new conversion. Conversions from the LTC2461/LTC2463 can be continuously read, see Figure 6. The R/W is 1 for a read.
PAGE 13
LTC2461/LTC2463 APPLICATIONS INFORMATION conversion cycle. The master issues a START, followed by the LTC2461/LTC2463 global address 1110111, and a write request. The LTC2461/LTC2463 will be selected and acknowledge the request. If desired, the master then sends the write byte to program the 30Hz or 60Hz mode. After the optional write byte, the master ends the write operation with a STOP.
PAGE 14
LTC2461/LTC2463 APPLICATIONS INFORMATION REFOUT and COMP The on-chip 1.25V precision reference is internally tied to the LTC2461/LTC2463 converter’s reference input and its output to the REFOUT pin. A 0.1μF capacitor should be placed on the REFOUT pin. It is possible to reduce this capacitor, but the transition noise increases. A 0.1μF capacitor should also be placed on the COMP pin. This pin is tied to an internal point in the reference and is used for stability.
PAGE 15
LTC2461/LTC2463 APPLICATIONS INFORMATION to the point that significant measurement errors exist. Additionally, for some applications, increasing the RS • CIN product too much may unacceptably attenuate the signal at frequencies of interest. For most applications, it is desirable to implement CIN as a high-quality 0.1µF ceramic capacitor and to set RS ≤ 1k. This capacitor should be located as close as possible to the actual IN+, IN– or IN package pin.
PAGE 16
LTC2461/LTC2463 APPLICATIONS INFORMATION 3 2 RS = 10k RS = 10k 0 RS = 0k RS = 0k 0 RS = 1k –1 –2 –2 –3 –1.25 0.25 0.75 –0.75 –0.25 DIFFERENTIAL INPUT VOLTAGE (V) –3 –1.25 1.25 24613 F10 INPUT SIGNAL ATTENUATION (dB) 0 VCC = 5V TA = 25°C –20 –40 –60 –80 0 2.5 5.0 7.5 1.00 1.25 1.50 INPUT SIGNAL FREQUENCY (MHz) 24613 F12 Figure 12. LTC2463 Input Signal Attentuation vs Frequency 0.25 0.75 –0.75 –0.25 DIFFERENTIAL INPUT VOLTAGE (V) 1.25 24613 F11 Figure 11.
PAGE 17
LTC2461/LTC2463 PACKAGE DESCRIPTION DD Package 12-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1725 Rev A) 0.70 ±0.05 3.50 ±0.05 2.10 ±0.05 2.38 ±0.05 1.65 ±0.05 PACKAGE OUTLINE 0.25 ± 0.05 0.45 BSC 2.25 REF RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 3.00 ±0.10 (4 SIDES) R = 0.115 TYP 7 0.40 ± 0.10 12 2.38 ±0.10 1.65 ± 0.10 PIN 1 NOTCH R = 0.20 OR 0.25 × 45° CHAMFER PIN 1 TOP MARK (SEE NOTE 6) 0.200 REF 0.75 ±0.05 6 1 0.23 ± 0.
PAGE 18
LTC2461/LTC2463 PACKAGE DESCRIPTION MS Package 12-Lead Plastic MSOP (Reference LTC DWG # 05-08-1668 Rev Ø) 0.889 ± 0.127 (.035 ± .005) 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) 4.039 ± 0.102 (.159 ± .004) (NOTE 3) 0.65 (.0256) BSC 0.42 ± 0.038 (.0165 ± .0015) TYP 12 11 10 9 8 7 RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) DETAIL “A” 3.00 ± 0.102 (.118 ± .004) (NOTE 4) 4.90 ± 0.152 (.193 ± .006) 0° – 6° TYP 0.406 ± 0.076 (.016 ± .003) REF GAUGE PLANE 0.53 ± 0.152 (.021 ± .006) DETAIL “A” 0.
PAGE 19
LTC2461/LTC2463 REVISION HISTORY REV DATE DESCRIPTION PAGE NUMBER A 5/11 Added “Synchronizing the LTC2461/LTC2463 with the Global Address Call” to the Applications Information section 12-13 24613fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use.
PAGE 20
LTC2461/LTC2463 TYPICAL APPLICATION 10µF VCC 0.1µF VCC 0.1µF VCC 1 IN+ IN– 1k 1k 9 0.1µF 0.1µF IN+ 12 REFOUT VCC 5k SCL 5 LTC2463 6 SDA IN– 3 10 A0 COMP REF– GND 0.1µF 2 8 7, 11, 4 0.