LTC2482 16-Bit ΔΣ ADC with Easy Drive Input Current Cancellation DESCRIPTION FEATURES n n n n n n n n n n n n Easy Drive™ Technology Enables Rail-to-Rail Inputs with Zero Differential Input Current Directly Digitizes High Impedance Sensors with Full Accuracy 600nV RMS Noise, Independent of VREF Operates with a Reference as Low as 100mV with 16-Bit Resolution GND to VCC Input/Reference Common Mode Range Simultaneous 50Hz/60Hz Rejection Mode 2ppm INL, No Missing Codes 1ppm Offset and 15ppm Total Unadjusted
LTC2482 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Notes 1, 2) Supply Voltage (VCC) to GND ...................... –0.3V to 6V Analog Input Voltage to GND ....... –0.3V to (VCC + 0.3V) Reference Input Voltage to GND .. –0.3V to (VCC + 0.3V) Digital Input Voltage to GND ........ –0.3V to (VCC + 0.3V) Digital Output Voltage to GND ...... –0.3V to (VCC + 0.3V) Operating Temperature Range LTC2482C ............................................... 0°C to 70°C LTC2482I ...........................................
LTC2482 CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4) PARAMETER CONDITIONS Input Common Mode Rejection DC 2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Note 5) l 140 dB Input Common Mode Rejection, 50Hz ±2% 2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Note 5) 2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Note 5) 2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Notes 5, 7) 2.
LTC2482 DIGITAL INPUTS AND DIGITAL OUTPUTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) SYMBOL PARAMETER CONDITIONS VIH High Level Input Voltage; CS, fO 2.7V ≤ VCC ≤ 5.5V (Note 16) l MIN VIL Low Level Input Voltage; CS, fO 2.7V ≤ VCC ≤ 5.5V l VIH High Level Input Voltage, SCK 2.7V ≤ VCC ≤ 5.5V (Note 10) l VIL Low Level Input Voltage, SCK 2.7V ≤ VCC ≤ 5.5V (Note 10) l TYP MAX UNITS VCC – 0.
LTC2482 TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) SYMBOL PARAMETER CONDITIONS fEOSC External Oscillator Frequency Range (Note 15) MAX UNITS l tHEO MIN 10 TYP 4000 kHz External Oscillator High Period l 0.125 100 μs tLEO External Oscillator Low Period l 0.125 tCONV_1 Conversion Time Simultaneous 50Hz/60Hz External Oscillator l l 144.
LTC2482 TYPICAL PERFORMANCE CHARACTERISTICS Integral Nonlinearity (VCC = 5V, VREF = 5V) 25°C 0 85°C –1 –2 1 2 INL (ppm OF VREF) –45°C 1 2 3 VCC = 5V VREF = 2.5V VIN(CM) = 1.25V fO = GND –45°C, 25°C, 90°C 0 –1 –2 –3 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 INPUT VOLTAGE (V) 2 –3 –1.25 2.5 –0.75 12 8 85°C 25°C 4 0 –45°C –4 –8 –12 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 INPUT VOLTAGE (V) VCC = 5V VREF = 5V VIN(CM) = 1.25V fO = GND 12 85°C 4 –45°C 0 –4 2 –0.75 –0.2 –0.
LTC2482 TYPICAL PERFORMANCE CHARACTERISTICS 0.1 0 –0.1 310 308 308 306 304 302 –0.2 –0.3 0 1 2 3 VREF (V) 300 –45 –30 –15 5 4 VCC = 4.1V VREF = 2.5V VIN = 0V VIN(CM) = GND fO = GND –20 –40 REJECTION (dB) REJECTION (dB) 75 90 –60 –80 VCC = 4.1V DC ±1.4V VREF = 2.5V IN+ = GND IN– = GND fO = GND TA = 25°C –60 –80 –140 1M 0 20 40 60 80 100 120 140 160 180 200 220 FREQUENCY AT VCC (Hz) 140 VCC = 2.7V 120 1.2 VCC = 5V 0.8 VCC = 2.
LTC2482 PIN FUNCTIONS GND (Pin 1): Ground. This pin should be tied to ground; however, in order to remain pin compatible with the LTC2480/LTC2484, this pin may be driven high or low. GND (Pin 8): Ground. Shared pin for analog ground, digital ground and reference ground. Should be connected directly to a ground plane through a minimum impedance. VCC (Pin 2): Positive Supply Voltage. Bypass to GND (Pin 8) with a 1μF tantalum capacitor in parallel with 0.
LTC2482 FUNCTIONAL BLOCK DIAGRAM 3 4 5 2 VCC VREF IN+ 3RD ORDER $3 ADC IN– IN– GND 1 REF+ IN+ SCK SD0 SERIAL INTERFACE CS 9 7 6 REF– fO AUTOCALIBRATION AND CONTROL 10 INTERNAL OSCILLATOR GND 8 2482 FD TEST CIRCUITS VCC 1.69k SDO SDO 1.
LTC2482 TIMING DIAGRAMS Timing Diagram Using Internal SCK CS t1 t2 SDO tKQMIN t3 tKQMAX SCK SLEEP DATA OUT CONVERSION 2482 TD1 Timing Diagram Using External SCK CS t1 t2 SDO t5 t6 tKQMIN tKQMAX t4 SCK SLEEP DATA OUT CONVERSION 2482 TD2 APPLICATIONS INFORMATION CONVERTER OPERATION CONVERT Converter Operation Cycle The LTC2482 is a low power, delta-sigma analog-to-digital converter with an easy-to-use 3-wire serial interface and automatic differential input current cancellation.
LTC2482 APPLICATIONS INFORMATION by two orders of magnitude. The part remains in the sleep state as long as CS is high. The conversion result is held indefinitely in a static shift register while the converter is in the sleep state. Once CS is pulled low, the device exits the low power mode and enters the data output state. If CS is pulled high before the first rising edge of SCK, the device returns to the low power sleep mode and the conversion result is still held in the internal static shift register.
LTC2482 APPLICATIONS INFORMATION Bit 23 (first output bit) is the end of conversion (EOC) indicator. This bit is available at the SDO pin during the conversion and sleep states whenever the CS pin is low. This bit is high during the conversion and goes low when the conversion is complete. Data is shifted out of the SDO pin under control of the serial clock (SCK) (see Figure 2).
LTC2482 APPLICATIONS INFORMATION A major advantage the delta-sigma converter offers over conventional type converters is an on-chip digital filter (commonly implemented as a SINC or Comb filter). For high resolution, low frequency applications, this filter is typically designed to reject line frequencies of 50Hz or 60Hz plus their harmonics. The filter rejection performance is directly related to the accuracy of the converter system clock. The LTC2482 incorporates a highly accurate on-chip oscillator.
LTC2482 APPLICATIONS INFORMATION Ease of Use The LTC2482 data output has no latency, filter settling delay or redundant data associated with the conversion cycle. There is a one-to-one correspondence between the conversion and the output data. Therefore, multiplexing multiple analog voltages is easy. The LTC2482 performs offset and full-scale calibrations every conversion cycle. This calibration is transparent to the user and has no effect on the cyclic operation described above.
LTC2482 APPLICATIONS INFORMATION SERIAL INTERFACE TIMING MODES The LTC2482’s 3-wire interface is SPI and MICROWIRE compatible. This interface offers several flexible modes of operation. These include internal/external serial clock, 2- or 3-wire I/O, single cycle or continuous conversion. The following sections describe each of these serial interface timing modes in detail.
LTC2482 APPLICATIONS INFORMATION 2.7V TO 5.5V 1μF 2 VCC 10 fO INT/EXT CLOCK LTC2482 REFERENCE VOLTAGE 0.1V TO VCC 3 VREF 9 SCK ANALOG INPUT TEST EOC (OPTIONAL) IN+ CS 5 IN– GND 3-WIRE SPI INTERFACE 7 SDO 4 6 8,1 CS TEST EOC BIT 23 BIT 22 BIT 21 BIT 20 SIG MSB EOC SDO Hi-Z BIT 19 BIT 18 BIT 17 BIT 16 BIT 4 TEST EOC BIT 0 LSB Hi-Z Hi-Z SCK (EXTERNAL) DATA OUTPUT CONVERSION CONVERSION 2482 F04 SLEEP SLEEP Figure 4. External Serial Clock, Single Cycle Operation 2.
LTC2482 APPLICATIONS INFORMATION clock cycles, or to remain compatible with higher resolution converters, the LTC2482’s digital interface will ignore extra clock edges seen during the next conversion period after the 24th and outputs “1” for the extra clock cycles. External Serial Clock, 2-Wire I/O This timing mode utilizes a 2-wire serial I/O interface. The conversion result is shifted out of the device by an externally generated serial clock (SCK) signal (see Figure 6).
LTC2482 APPLICATIONS INFORMATION When testing EOC, if the conversion is complete (EOC = 0), the device will exit the low power mode during the EOC test. In order to allow the device to return to the low power sleep state, CS must be pulled high before the first rising edge of SCK. In the internal SCK timing mode, SCK goes high and the device begins outputting data at time tEOCtest after the falling edge of CS (if EOC = 0) or tEOCtest after EOC goes low (if CS is low during the falling edge of EOC).
LTC2482 APPLICATIONS INFORMATION A similar situation may occur during the sleep state when CS is pulsed high-low-high in order to test the conversion status. If the device is in the sleep state (EOC = 0), SCK will go low. Once CS goes high (within the time period defined above as tEOCtest), the internal pull-up is activated. For a heavy capacitive load on the SCK pin, the internal pull-up may not be adequate to return SCK to a high level before CS goes low again.
LTC2482 APPLICATIONS INFORMATION 2.7V TO 5.5V 1μF 2 VCC 10 fO INT/EXT CLOCK VCC LTC2482 REFERENCE VOLTAGE 0.1V TO VCC 3 10k VREF SDO ANALOG INPUT 9 SCK 4 IN+ 5 IN– CS GND 2-WIRE SPI INTERFACE 7 6 8,1 CS BIT 23 SDO EOC BIT 22 BIT 21 BIT 20 SIG MSB BIT 19 BIT 18 BIT 17 BIT 16 BIT 4 BIT 0 LSB SCK (INTERNAL) CONVERSION DATA OUTPUT CONVERSION 2482 F09 Figure 9.
LTC2482 APPLICATIONS INFORMATION An alternate solution is to reduce the edge rate of the control signals. It should be noted that using very slow edges will increase the converter power supply current during the transition time. The differential input architecture reduces the converter’s sensitivity to ground currents. Particular attention must be given to the connection of the fO signal when the LTC2482 is used with an external conversion clock.
LTC2482 APPLICATIONS INFORMATION When using the internal oscillator, the LTC2482’s front-end switched-capacitor network is clocked at 123kHz corresponding to an 8.1μs sampling period. Thus, for settling errors of less than 1ppm, the driving source impedance should be chosen such that τ ≤ 8.1μs/14 = 580ns. When an external oscillator of frequency fEOSC is used, the sampling period is 2.5/fEOSC and, for a settling error of less than 1ppm, τ ≤ 0.178/fEOSC.
LTC2482 APPLICATIONS INFORMATION RSOURCE IN+ VINCM + 0.5VIN CIN CPAR 20pF LTC2482 RSOURCE IN– VINCM – 0.5VIN CIN CPAR 20pF 2482 F11 Figure 11. An RC Network at IN+ and IN– +FS ERROR (ppm) 80 VCC = 5V = 5V 60 VREF VIN+ = 3.75V – = 1.25V 40 VIN fO = GND 20 TA = 25°C In addition to the input sampling charge, the input ESD protection diodes have a temperature dependent leakage current. This current, nominally 1nA (±10nA max), results in a small offset shift.
LTC2482 APPLICATIONS INFORMATION resistance is 1.1MΩ and the resulting full-scale error is 0.46ppm for each ohm of source resistance driving the VREF pin. When fO is driven by an external oscillator with a frequency fEOSC (external conversion clock operation), the typical differential reference resistance is 0.33 • 1012/ fEOSC Ω and each ohm of source resistance driving the VREF pin will result in 1.53 • 10–6 • fEOSCppm gain error.
LTC2482 APPLICATIONS INFORMATION INL (ppm OF VREF) 10 Output Data Rate VCC = 5V 8 VREF = 5V VIN(CM) = 2.5V 6 T = 25°C A 4 CREF = 10μF R = 1k 2 R = 500Ω 0 R = 100Ω –2 –4 –6 –8 –10 –0.5 –0.3 0.1 –0.1 VIN/VREF (V) 0.3 0.5 2482 F18 Figure 18. INL vs Differential Input Voltage and Reference Source Resistance for CREF > 1μF In applications where the reference and input common mode voltages are different, extra errors are introduced.
LTC2482 APPLICATIONS INFORMATION 3500 VIN(CM) = VREF(CM) VCC = VREF = 5V VIN = 0V fO = EXT CLOCK 40 3000 +FS ERROR (ppm OF VREF) OFFSET ERROR (ppm OF VREF) 50 30 TA = 85°C 20 10 VIN(CM) = VREF(CM) VCC = VREF = 5V fO = EXT CLOCK 2500 TA = 85°C 2000 1500 TA = 25°C 1000 0 500 TA = 25°C 0 –10 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2482 F20 2482 F19 Figure 19.
LTC2482 APPLICATIONS INFORMATION degradation in the converter accuracy and linearity. Typical measured performance curves for output data rates up to 100 readings per second are shown in Figures 19 to 24. In order to obtain the highest possible level of accuracy from this converter at output data rates above 20 readings per second, the user is advised to maximize the power supply voltage used and to limit the maximum ambient operating temperature.
LTC2482 APPLICATIONS INFORMATION If the fO pin is driven by an external oscillator of frequency fEOSC, Figure 26 can still be used for noise calculation if the x-axis is scaled by fEOSC/307200. For large values of the ratio fEOSC/307200, the Figure 26 plot accuracy begins to decrease, but at the same time the LTC2482 noise floor rises and the noise contribution of the driving amplifiers lose significance.
LTC2482 APPLICATIONS INFORMATION NORMAL MODE REJECTION (dB) 0 MEASURED DATA CALCULATED DATA –20 –40 VCC = 5V VREF = 5V VIN(CM) = 2.5V VIN(P-P) = 5V TA = 25°C –60 –80 –100 –120 0 20 40 60 80 100 120 140 INPUT FREQUENCY (Hz) 160 180 200 220 2482 F29 Figure 29. Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 100% Full Scale order modulator resolves this problem and guarantees a predictable stable behavior at input signal levels of up to 150% of full scale.
LTC2482 PACKAGE DESCRIPTION DD Package 10-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1699) 0.675 ±0.05 3.50 ±0.05 1.65 ±0.05 2.15 ±0.05 (2 SIDES) PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 2.38 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 3.00 ±0.10 (4 SIDES) R = 0.115 TYP 6 0.38 ± 0.10 10 1.65 ± 0.10 (2 SIDES) PIN 1 TOP MARK (SEE NOTE 6) (DD) DFN 1103 5 0.200 REF 1 0.75 ±0.05 0.00 – 0.05 0.25 ± 0.05 0.50 BSC 2.38 ±0.10 (2 SIDES) BOTTOM VIEW—EXPOSED PAD NOTE: 1.
LTC2482 REVISION HISTORY (Revision history begins at Rev C) REV DATE DESCRIPTION C 7/10 Revised Typical Application drawing PAGE NUMBER 1, 32 Added Note 16 4, 5 2482fc Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC2482 TYPICAL APPLICATION 5V C8 1μF 0.1μF 100 METERS 1k 1% VIN+ 1μF REF VCC LTC2482 CS SCK SDO VIN– 1k 1% REMOTE SENSOR C7 0.1μF fO GND GND 0.1μF 2482 F30 Figure 30. Differential Input Current Cancellation Enables Direct Digitization of Remote Sensors 5 12 3 NUMBER OF READINGS (%) INTEGRAL NONLINEARITY THROUGH 100 METERS OF WIRE AND A 1kΩ, 1μF RC NETWORK 4 INL (LSB) 2 1 0 –1 –2 –3 RMS NOISE = 630nV AVERAGE = –3.5μV 10 2500 CONSECUTIVE READINGS 8 6 4 2 –4 –5 0 0.5 1.
