Datasheet

ManualsBrandsLinear Technology ManualsDAC - Digital to AnalogD/A Converter IC 16bit MSOP-

LTC2602/LTC2612/LTC2622

2602fa

, LTC and LT are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

BLOCK DIAGRA

DESCRIPTIO

APPLICATIO S

FEATURES

OUT A

REF

CS/LD

SCK

OUT B

GND

SDI

2602 BD01

7 6

16-BIT

DAC A

16-BIT

DAC B

DECODE

CONTROL

LOGIC

24-BIT SHIFT REGISTER

The LTC

2602/LTC2612/LTC2622 are dual 16-,14- and

12-bit, 2.5V-to-5.5V rail-to-rail voltage-output DACs, in a

tiny 8-lead MSOP package. They have built-in high per-

formance output buffers and are guaranteed monotonic.

These parts establish advanced performance standards

for output drive, crosstalk and load regulation in single-

supply, voltage output multiples.

The parts use a simple SPI/MICROWIRE™ compatible

3-wire serial interface which can be operated at clock

rates up to 50MHz.

The LTC2602/LTC2612/LTC2622 incorporate a power-

on reset circuit. During power-up, the voltage outputs

rise less than 10mV above zero scale, and after power-

up, they stay at zero scale until a valid write and update

take place.

■

Smallest Pin-Compatible Dual DACs:

LTC2602: 16-Bits

LTC2612: 14-Bits

LTC2622: 12-Bits

■

Guaranteed 16-Bit Monotonic Over Temperature

■

Wide 2.5V to 5.5V Supply Range

■

Low Power Operation: 300µA per DAC at 3V

■

Individual Channel Power-Down to 1µA, Max

■

Ultralow Crosstalk between DACs (30µV)

■

High Rail-to-Rail Output Drive (±15mA)

■

Double-Buffered Data Latches

■

Pin-Compatible 10-Bit Version (LTC1661)

■

Tiny 8-Lead MSOP Package

■

Mobile Communications

■

Process Control and Industrial Automation

■

Instrumentation

■

Automatic Test Equipment

Differential Nonlinearity (DNL)(LTC2602)

CODE

0 16384 32768 49152 65535

ERROR (LSB)

2602 TA01

1.0

0.8

0.6

0.4

0.2

–0.2

–0.4

–0.6

–0.8

–1.0

= 5V

REF

= 4.096V

LTC2602

Dual 16-/14-/12-Bit

Rail-to-Rail DACs in 8-Lead MSOP

Downloaded from Arrow.com.

Summary of content (16 pages)

PAGE 1
LTC2602/LTC2612/LTC2622 Dual 16-/14-/12-Bit Rail-to-Rail DACs in 8-Lead MSOP U FEATURES DESCRIPTIO ■ The LTC®2602/LTC2612/LTC2622 are dual 16-,14- and 12-bit, 2.5V-to-5.5V rail-to-rail voltage-output DACs, in a tiny 8-lead MSOP package. They have built-in high performance output buffers and are guaranteed monotonic. ■ ■ ■ ■ ■ ■ ■ ■ ■ Smallest Pin-Compatible Dual DACs: LTC2602: 16-Bits LTC2612: 14-Bits LTC2622: 12-Bits Guaranteed 16-Bit Monotonic Over Temperature Wide 2.5V to 5.
PAGE 2
LTC2602/LTC2612/LTC2622 W U U W W W AXI U U ABSOLUTE PACKAGE/ORDER I FOR ATIO RATI GS (Note 1) Any Pin to GND ........................................... – 0.3V to 6V Any Pin to VCC ........................................................ –6V to 0.3V Maximum Junction Temperature ......................... 125°C Operating Temperature Range LTC2602C/LTC2612C/LTC2622C .......... 0°C to 70°C LTC2602I/LTC2612I/LTC2622I .......... – 40°C to 85°C Storage Temperature Range ................
PAGE 3
LTC2602/LTC2612/LTC2622 ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 2.5V to 5.5V, VREF ≤ VCC, VOUT unloaded, unless otherwise noted. LTC2602/LTC2612/LTC2622 MIN TYP MAX –80 SYMBOL PSRR PARAMETER Power Supply Rejection Ratio CONDITIONS VCC = 5V ±10% ROUT DC Output Impedance VREF = VCC = 5V, Midscale; –15mA ≤ IOUT ≤ 15mA VREF = VCC = 2.5V, Midscale; –7.5mA ≤ IOUT ≤ 7.
PAGE 4
LTC2602/LTC2612/LTC2622 WU TI I G CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (See Figure 1) (Note 6) SYMBOL PARAMETER LTC2602/LTC2612/LTC2622 MIN TYP MAX CONDITIONS UNITS VCC = 2.5V to 5.
PAGE 5
LTC2602/LTC2612/LTC2622 U W TYPICAL PERFOR A CE CHARACTERISTICS (LTC2602) DNL vs Temperature INL vs VREF 1.0 DNL vs VREF 32 VCC = 5V VREF = 4.096V 0.8 0.6 1.5 VCC = 5.5V 24 VCC = 5.5V 1.0 16 0.2 0 –0.2 0 –8 DNL (NEG) 0.5 INL (POS) 8 DNL (LSB) DNL (POS) INL (LSB) DNL (LSB) 0.4 INL (NEG) DNL (POS) 0 DNL (NEG) –0.5 –0.4 –16 –0.6 –1.0 –24 –0.8 –1.0 –50 –30 –10 10 30 50 TEMPERATURE (°C) 70 –32 90 0 1 2 3 VREF (V) 4 2602 G23 5 –1.
PAGE 6
LTC2602/LTC2612/LTC2622 U W TYPICAL PERFOR A CE CHARACTERISTICS (LTC2622) 2.0 1.0 VCC = 5V VREF = 4.096V 1.5 Settling to ±1LSB Differential Nonlinearity (DNL) Integral Nonlinearity (INL) VCC = 5V VREF = 4.096V 0.8 0.6 1.0 DNL (LSB) 0.5 INL (LSB) 6.8µs 0.4 0 –0.5 VOUT 1mV/DIV 0.2 0 CS/LD 2V/DIV –0.2 –0.4 –1.0 –0.6 –1.5 –2.0 –1.0 0 1024 2048 CODE 3072 4095 2602 G33 2µs/DIV –0.8 0 1024 2048 CODE 3072 VCC = 5V, VREF = 4.
PAGE 7
LTC2602/LTC2612/LTC2622 U W TYPICAL PERFOR A CE CHARACTERISTICS (LTC2602/LTC2612/LTC2622) ICC Shutdown vs VCC 450 0.3 400 0.2 350 0.1 300 ICC (nA) GAIN ERROR (%FSR) Gain Error vs VCC 0.4 0 –0.1 Large-Signal Settling VOUT 0.5V/DIV 250 200 VREF = VCC = 5V 1/4-SCALE TO 3/4-SCALE 150 –0.2 100 –0.3 2.5µs/DIV 50 –0.4 2.5 3 3.5 4 VCC (V) 4.5 5 5.5 0 2.5 3 3.5 4 VCC (V) 4.5 5 2602 G09 5.
PAGE 8
LTC2602/LTC2612/LTC2622 U W TYPICAL PERFOR A CE CHARACTERISTICS (LTC2602/LTC2612/LTC2622) Output Voltage Noise, 0.1Hz to 10Hz Short-Circuit Output Current vs VOUT (Sourcing) Short-Circuit Output Current vs VOUT (Sinking) 50 0 V CC = 5.5V V REF = 5.6V CODE = 0 V OUT SWEPT 0V TO V CC 40 –10 30 10mA/DIV 10mA/DIV VOUT 10µV/DIV 20 10 0 1 2 3 4 5 6 SECONDS 7 8 9 V CC = 5.5V V REF = 5.
PAGE 9
LTC2602/LTC2612/LTC2622 U U U PIN FUNCTIONS CS/LD (Pin 1): Serial Interface Chip Select/Load Input. When CS/LD is low, SCK is enabled for shifting data on SDI into the register. When CS/LD is taken high, SCK is disabled and the specified command (see Table 1) is executed. SCK (Pin 2): Serial Interface Clock Input. CMOS and TTL compatible. SDI (Pin 3): Serial Interface Data Input. Data is applied to SDI for transfer to the device at the rising edge of SCK.
PAGE 10
LTC2602/LTC2612/LTC2622 U OPERATIO Power-On Reset The LTC2602/LTC2612/LTC2622 clear the outputs to zero scale when power is first applied, making system initialization consistent and repeatable. For some applications, downstream circuits are active during DAC power-up, and may be sensitive to nonzero outputs from the DAC during this time.
PAGE 11
LTC2602/LTC2612/LTC2622 U OPERATIO INPUT WORD (LTC2602) COMMAND C3 C2 C1 C0 ADDRESS A3 A2 A1 DATA (16 BITS) A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB LSB 2602 TBL01 INPUT WORD (LTC2612) COMMAND C3 C2 C1 C0 ADDRESS A3 A2 A1 DATA (14 BITS + 2 DON’T-CARE BITS) A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB X X LSB 2602 TBL02 INPUT WORD (LTC2622) COMMAND C3 C2 C1 C0 ADDRESS A3 A2 A1 DATA (12 BITS + 4 DON’T-CARE BITS) A0 D11 D10 D9 D8 D7 D6 D5 D4
PAGE 12
LTC2602/LTC2612/LTC2622 U OPERATIO Board Layout The excellent load regulation and DC crosstalk performance of these devices is achieved in part by keeping “signal” and “power” grounds separated internally and by reducing shared internal resistance. The GND pin functions both as the node to which the reference and output voltages are referred and as a return path for power currents in the device.
PAGE 13
Downloaded from Arrow.com. SDI SCK CS/LD X 1 X 2 3 X 4 X C3 SDI C2 2 C1 3 DON’T CARE X 5 X 6 X 7 COMMAND WORD 1 SCK CS/LD X C0 4 8 A1 7 ADDRESS WORD A2 6 A0 8 D15 9 D14 10 D12 12 D11 13 D10 14 24-BIT INPUT WORD D13 11 D9 15 D7 17 DATA WORD D8 16 D6 18 C1 11 COMMAND WORD C2 10 C0 12 A3 A2 14 A1 15 ADDRESS WORD 13 A0 16 D15 17 D14 18 D13 19 D12 20 D11 21 D10 22 Figure 2b.
PAGE 14
LTC2602/LTC2612/LTC2622 U OPERATIO VREF = VCC VREF = VCC POSITIVE FSE OUTPUT VOLTAGE OUTPUT VOLTAGE INPUT CODE OUTPUT VOLTAGE (c) 0 0V NEGATIVE OFFSET INPUT CODE 32,768 INPUT CODE 65,535 (a) 2600 F03 (b) Figure 3. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Codes Near Full Scale 2602fa 14 Downloaded from Arrow.com.
PAGE 15
LTC2602/LTC2612/LTC2622 U PACKAGE DESCRIPTIO MS8 Package 8-Lead Plastic MSOP (Reference LTC DWG # 05-08-1660) 0.889 ± 0.127 (.035 ± .005) 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) 0.42 ± 0.038 (.0165 ± .0015) TYP 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 0.65 (.0256) BSC 8 7 6 5 0.52 (.0205) REF RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) 3.00 ± 0.102 (.118 ± .004) (NOTE 4) 4.90 ± 0.152 (.193 ± .006) DETAIL “A” 0° – 6° TYP GAUGE PLANE 0.53 ± 0.152 (.021 ± .006) DETAIL “A” 1 2 3 4 1.10 (.
PAGE 16
LTC2602/LTC2612/LTC2622 RELATED PARTS PART NUMBER LTC1458/LTC1458L DESCRIPTION Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality LTC1654 LTC1655/LTC1655L LTC1657/LTC1657L LTC1660/LTC1665 LTC1661 LTC1821 LTC2600/LTC2610/ LTC2620 Dual 14-Bit Rail-to-Rail VOUT DAC Single 16-Bit VOUT DAC with Serial Interface in SO-8 Parrallel 5V/3V 16-Bit VOUT DAC Octal 10/8-Bit VOUT DAC in 16-Pin Narrow SSOP Dual 10-Bit VOUT DAC in 8-Lead MSOP Package Parallel 16-Bit Voltage Output DAC Octal 16/14/12-Bit Rail-t