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LTC2609/LTC2619/LTC2629

26091929fb

Block Diagram

Description

Quad 16-/14-/12-Bit

Rail-to-Rail DACs with

C Interface

The LTC

2609/LTC2619/LTC2629 are quad 16-, 14- and 12-

bit, 2.7V to 5.5V rail-to-rail voltage output DACs in a 16-lead

SSOP package. They have built-in high performance output

buffers and are guaranteed monotonic.

These parts establish new board-density benchmarks for

16- and 14-bit DACs and advance performance standards

for output drive and load regulation in single-supply, volt-

age-output DACs.

The parts use a 2-wire, I

C compatible serial interface. The

LTC2609/LTC2619/LTC2629 operate in both the standard

mode (clock rate of 100kHz) and the fast mode (clock

rate of 400kHz).

The LTC2609/LTC2619/LTC2629 incorporate a power-on

reset circuit. During power-up, the voltage outputs rise less

than 10mV above zero-scale; after power-up, they stay at

zero-scale until a valid write and update take place. The

power

-on

reset circuit resets the LTC2609-1/LTC2619-1/

LTC2629-1 to mid-scale. The voltage outputs stay at mid-

scale until a valid write and update take place.

Differential Nonlinearity

(LTC2609)

Features

applications

Smallest Pin-Compatible Quad DACs:

LTC2609: 16 Bits

LTC2619: 14 Bits

LTC2629: 12 Bits

Guaranteed Monotonic Over Temperature

Separate Reference Inputs

27 Selectable Addresses

400kHz I

™

Interface

Wide 2.7V to 5.5V Supply Range

Low Power Operation: 250µA per DAC at 3V

Individual Channel Power Down to 1µA (Max)

High Rail-to-Rail Output Drive (±15mA, Min)

Ultralow Crosstalk Between DACs (5µV)

LTC2609/LTC2619/LTC2629: Power-On Reset to

Zero-Scale

LTC2609-1/LTC2619-1/LTC2629-1: Power-On Reset

to Mid-Scale

Tiny 16-Lead Narrow SSOP Package

Mobile Communications

Process Control and Industrial Automation

Automatic Test Equipment and Instrumentation

INTERFACE

ADDRESS

DECODE

LOGIC

32-BIT SHIFT REGISTER

DAC

INPUT

SDA

2609 BD

REFB

SCL

OUTB

OUTA

REFA

REFLO

GND

DAC A

DAC B

REFC

OUTC

OUTD

CA2

CA1

CA0

REFD

DAC D

DAC C

CONTROL

LOGIC

CODE

0 16384 32768 49152 65535

DNL (LSB)

2609 G02

1.0

0.8

0.6

0.4

0.2

–0.2

–0.4

–0.6

–0.8

–1.0

= 5V

REF

= 4.096V

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

Protected by U.S. Patents including 5396245. Patent pending.

Summary of content (22 pages)

PAGE 1
LTC2609/LTC2619/LTC2629 Quad 16-/14-/12-Bit Rail-to-Rail DACs with I2C Interface Description Features n n n n n n n n n n n n n Smallest Pin-Compatible Quad DACs: LTC2609: 16 Bits LTC2619: 14 Bits LTC2629: 12 Bits Guaranteed Monotonic Over Temperature Separate Reference Inputs 27 Selectable Addresses 400kHz I2C™ Interface Wide 2.7V to 5.
PAGE 2
LTC2609/LTC2619/LTC2629 Absolute Maximum Ratings (Note 1) Any Pin to GND............................................. –0.3V to 6V Any Pin to VCC ............................................ –6V to 0.3V Maximum Junction Temperature........................... 125°C Storage Temperature Range................... –65°C to 125°C Lead Temperature (Soldering, 10 sec)................... 300°C Operating Temperature Range: LTC2609C/LTC2619C/LTC2629C LTC2609C-1/LTC2619C-1/LTC2629C-1.....
PAGE 3
LTC2609/LTC2619/LTC2629 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. REFA = REFB = REFC = REFD = 4.096V (VCC = 5V), REFA = REFB = REFC = REFD = 2.048V (VCC = 2.7V). REFLO = 0V, VOUT = unloaded, unless otherwise noted.
PAGE 4
LTC2609/LTC2619/LTC2629 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. REFA = REFB = REFC = REFD = 4.096V (VCC = 5V), REFA = REFB = REFC = REFD = 2.048V (VCC = 2.7V). REFLO = 0V, VOUT = unloaded, unless otherwise noted.
PAGE 5
LTC2609/LTC2619/LTC2629 Timing Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (See Figure 1) (Notes 8, 9) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 400 kHz VCC = 2.7V to 5.5V fSCL SCL Clock Frequency l 0 tHD(STA) Hold Time (Repeated) Start Condition l 0.6 µs tLOW Low Period of the SCL Clock Pin l 1.3 µs tHIGH High Period of the SCL Clock Pin l 0.
PAGE 6
LTC2609/LTC2619/LTC2629 Typical Performance Characteristics LTC2609 Integral Nonlinearity (INL) 32 Differential Nonlinearity (DNL) 1.0 VCC = 5V VREF = 4.096V 24 16 0.4 –8 0.2 INL (LSB) DNL (LSB) 0 0 –0.2 –0.4 –16 16384 32768 CODE 49152 –1.0 65535 0 16384 32768 CODE 49152 2609 G01 –10 10 30 50 TEMPERATURE (°C) 70 90 DNL vs VREF 1.5 VCC = 5.5V 24 0.6 VCC = 5.5V 1.0 16 0.4 DNL (POS) 0.2 INL (LSB) DNL (LSB) –30 2609 G03 INL vs VREF 32 VCC = 5V VREF = 4.096V 0 –0.
PAGE 7
LTC2609/LTC2619/LTC2629 Typical Performance Characteristics LTC2619 Integral Nonlinearity (INL) 8 Differential Nonlinearity (DNL) 1.0 VCC = 5V VREF = 4.096V 6 0.6 0.4 2 DNL (LSB) INL (LSB) VCC = 5V VREF = 4.096V 0.8 4 0 –2 VOUT 100µV/DIV 0.2 0 SCL 2V/DIV –0.2 –0.4 –4 –0.6 –6 –8 Settling to ±1LSB 4096 8192 CODE 12288 –1.0 16383 8.9µs 2µs/DIV –0.8 0 9TH CLOCK OF 3RD DATA BYTE 0 4096 8192 CODE 12288 2609 G09 2609 G11 VCC = 5V, VREF = 4.
PAGE 8
LTC2609/LTC2619/LTC2629 Typical Performance Characteristics LTC2609/LTC2619/LTC2629 Current Limiting 0.08 CODE = MID-SCALE 0.8 VREF = VCC = 5V 0.06 ΔVOUT (mV) 0 VREF = VCC = 3V –0.04 2 0.2 0 –0.2 VREF = VCC = 5V –0.4 VREF = VCC = 5V –0.06 CODE = MID-SCALE 0.4 0.02 –0.02 Offset Error vs Temperature 3 0.6 VREF = VCC = 3V 0.04 ΔVOUT (V) Load Regulation 1.0 VREF = VCC = 3V –0.6 –0.08 OFFSET ERROR (mV) 0.10 20 30 –1.
PAGE 9
LTC2609/LTC2619/LTC2629 Typical Performance Characteristics LTC2609/LTC2619/LTC2629 Large-Signal Response Mid-Scale Glitch Impulse Power-On Reset Glitch TRANSITION FROM MS-1 TO MS VOUT 10mV/DIV VOUT 0.5V/DIV SCL 2V/DIV VREF = VCC = 5V 1/4 SCALE TO 3/4 SCALE 2609 G23 2.5µs/DIV TRANSITION FROM MS TO MS-1 2.5µs/DIV Headroom at Rails vs Output Current 4mV PEAK VOUT 10mV/DIV 2609 G24 250µs/DIV Power-On Reset to Mid-Scale 5.0 1.7 2.5 ICC (mA) VOUT (V) 1.6 3V SOURCING 3.0 1V/DIV 2.0 1.5 1.
PAGE 10
LTC2609/LTC2619/LTC2629 Typical Performance Characteristics LTC2609/LTC2619/LTC2629 Output Voltage Noise, 0.1Hz to 10Hz Multiplying Bandwidth 0 –3 –6 –9 –12 VOUT 10µV/DIV dB –15 –18 –21 –24 –27 VCC = 5V VREF (DC) = 2V VREF (AC) = 0.2VP-P CODE = FULL SCALE –30 –33 –36 0 2 3 4 5 6 SECONDS 7 8 9 10 2609 G30 1M 10k 100k FREQUENCY (Hz) 1k 1 2609 G29 Short-Circuit Output Current vs VOUT (Sinking) 50 0 VCC = 5.5V VREF = 5.6V CODE = 0 VOUT SWEPT 0V TO VCC 40 30 20 10 0 VCC = 5.
PAGE 11
LTC2609/LTC2619/LTC2629 Pin Functions GND (Pin 1): Analog Ground. REFLO (Pin 2): Reference Low. The voltage at this pin sets the zero-scale (ZS) voltage of all DACs. This pin can be raised up to 1V above ground at VCC = 5V or 100mV above ground at VCC = 3V. REFA to REFD (Pins 3, 6, 12, 15): Reference Voltage Inputs for each DAC. REFx sets the full-scale voltage of the DACs. REFLO ≤ REFx ≤ VCC . VOUTA to VOUTD (Pins 4, 5, 13, 14): DAC Analog Voltage Outputs. The output range is from REFLO to REFx.
PAGE 12
LTC2609/LTC2619/LTC2629 Block Diagram REFLO REFA 2 GND 1 VCC 16 REFD 15 VOUTD DAC A DAC REGISTER INPUT REGISTER INPUT REGISTER DAC REGISTER DAC D DAC B INPUT REGISTER INPUT REGISTER DAC REGISTER VOUTA 4 DAC REGISTER 3 DAC C VOUTB 5 REFB 14 VOUTC 13 REFC 12 6 CONTROL LOGIC 32-BIT SHIFT REGISTER CA0 11 SCL 8 SDA 9 I2C INTERFACE ADDRESS DECODE LOGIC CA1 10 CA2 7 2609 BD 26091929fb 12
PAGE 13
LTC2609/LTC2619/LTC2629 Test Circuits Test Circuit 1 Test Circuit 2 VDD 100Ω RINH/RINL/RINF CAn CAn VIH(CAn)/VIL(CAn) GND 2609 TC Timing Diagram SDA tf tLOW tSU(DAT) tr tf tHD(STA) tSP tr tBUF SCL S tHD(STA) tHD(DAT) tHIGH tSU(STA) S tSU(STO) P S 2609 F01 ALL VOLTAGE LEVELS REFER TO VIH(MIN) AND VIL(MAX) LEVELS Figure 1 26091929fb 13
PAGE 14
LTC2609/LTC2619/LTC2629 Operation Power-On Reset The LTC2609/LTC2619/LTC2629 clear the outputs to zero-scale when power is first applied, making system initialization consistent and repeatable. The LTC2609-1/ LTC2619‑1/LTC2629-1 set the voltage outputs to mid-scale when power is first applied. For some applications, downstream circuits are active during DAC power-up and may be sensitive to nonzero outputs from the DAC during this time.
PAGE 15
LTC2609/LTC2619/LTC2629 Operation during the Acknowledge clock pulse so that it remains a stable LOW during the HIGH period of this clock pulse. The LTC2609/LTC2619/LTC2629 respond to a write by a master in this manner. The LTC2609/LTC2619/LTC2629 do not acknowledge a read (retains SDA HIGH during the period of the Acknowledge clock pulse). Chip Address The state of CA0, CA1 and CA2 decides the slave address of the part.
PAGE 16
LTC2609/LTC2619/LTC2629 Operation Write Word Protocol for LTC2609/LTC2619/LTC1629 S SLAVE ADDRESS W A 1ST DATA BYTE A 2ND DATA BYTE C2 C1 C0 A3 A2 3RD DATA BYTE A P INPUT WORD Input Word (LTC2609) C3 A A1 A0 D15 D14 D13 D12 D11 D10 D9 1ST DATA BYTE D8 D7 D6 D5 2ND DATA BYTE D4 D3 D2 D1 D0 3RD DATA BYTE Input Word (LTC2619) C3 C2 C1 C0 A3 A2 A1 A0 D13 D12 D11 D10 D9 1ST DATA BYTE D8 D7 D6 D5 D4 D3 2ND DATA BYTE D2 D1 D0 X X X X 3RD DATA BYTE Input Word (LTC2629)
PAGE 17
LTC2609/LTC2619/LTC2629 Operation main bias generation circuit block has been automatically shut down in addition to the individual DAC amplifiers and reference inputs. In this case, the power-up delay time is 12µs (for VCC = 5V) or 30µs (for VCC = 3V). Voltage Output The rail-to-rail amplifier has guaranteed load regulation when sourcing or sinking up to 15mA at 5V (7.5mA at 2.7V).
PAGE 18
X = DON’T CARE 2 1 SCL 3 SA4 4 SA3 SA3 5 SA2 SA2 6 SA1 SA1 SLAVE ADDRESS SA4 7 SA0 SA0 8 WR 1 C3 2 C2 C2 3 C1 C1 4 C0 C0 5 A3 A3 COMMAND 6 A2 A2 7 A1 A1 8 A0 A0 9 ACK 1 D15 2 D14 3 D13 4 5 D11 MS DATA D12 6 D10 7 D9 8 D8 9 ACK 1 D7 2 D6 3 D5 Figure 4.
PAGE 19
NEGATIVE OFFSET 0V OUTPUT VOLTAGE 0 (5a) 32, 768 INPUT CODE 65, 535 (5c) INPUT CODE Figure 5. Effects of Rail-to-Rail Operation on a DAC Transfer Curve.
PAGE 20
LTC2609/LTC2619/LTC2629 Typical Application Demo Board Schematic—Onboard 20-Bit ADC Measures Key Performance Parameters REFA JP3 2 1 3 A B 4 5 C 6 1 C1 VCC 0.1µF REFB JP4 REFC JP5 2 1 3 A B 4 5 C 6 REFD JP6 2 1 3 A B 4 5 C 6 ADC REF JP7 2 1 3 A B 4 5 C 6 VREF 2 3 A B 5 C 6 4 VCC 5VREF 16 4.096VREF VCC 11 10 7 9 I2C 8 REFLO 2 4 C6 0.1µF 3 C8 0.1µF VIN VOUT NC NC 6 5 GND GND VIN C10 0.1µF E6 E7 E8 E9 VREF C4 0.1µF C3 100pF C7 1µF 6.3V 4.
PAGE 21
LTC2609/LTC2619/LTC2629 Revision History REV DATE DESCRIPTION A 11/09 Update Manufacturer’s Information on Typical Application 1 Revise Receiver Input Hysteresis Conditions 3 Revise Block Diagram 7 Revise Figure 1.
PAGE 22
LTC2609/LTC2619/LTC2629 Package Description GN Package 16-Lead Plastic SSOP (Reference LTC DWG # 05-08-1641) .189 – .196* (4.801 – 4.978) .045 p.005 16 15 14 13 12 11 10 9 .254 MIN .009 (0.229) REF .150 – .165 .229 – .244 (5.817 – 6.198) .0165 p.0015 .150 – .157** (3.810 – 3.988) .0250 BSC RECOMMENDED SOLDER PAD LAYOUT 1 .015 p .004 s 45o (0.38 p 0.10) .007 – .0098 (0.178 – 0.249) 2 3 4 5 6 7 .0532 – .0688 (1.35 – 1.75) 8 .004 – .0098 (0.102 – 0.249) 0o – 8o TYP .016 – .050 (0.406 – 1.