Datasheet

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LTC2600/LTC2610/LTC2620

2600fe

BLOCK DIAGRAM

DESCRIPTION

Octal 16-/14-/12-Bit

Rail-to-Rail DACs in 16-Lead SSOP

The LTC

2600/LTC2610/LTC2620 are octal 16-, 14- and

12-bit, 2.5V-to-5.5V rail-to-rail voltage-output DACs in

16-lead narrow SSOP and 20-lead 4mm × 5mm QFN

packages. They have built-in high performance output

buffers and are guaranteed monotonic.

These parts establish new board-density benchmarks for

16- and 14-bit DACs and advance performance standards for

output drive, crosstalk and load regulation in single-supply,

voltage-output multiples.

The parts use a simple SPI/MICROWIRE compatible 3-wire

serial interface which can be operated at clock rates up

to 50MHz. Daisychain capability and a hardware CLR

function are included.

The LTC2600/LTC2610/LTC2620 incorporate a power-on

reset circuit. During power-up, the voltage outputs rise less

than 10mV above zero-scale; and after power-up, they stay

at zero-scale until a valid write and update take place.

FEATURES

APPLICATIONS

Mobile Communications

Process Control and Industrial Automation

Instrumentation

Automatic Test Equipment

Smallest Pin-Compatible Octal DACs:

LTC2600: 16 Bits

LTC2610: 14 Bits

LTC2620: 12 Bits

Guaranteed 16-Bit Monotonic Over Temperature

Wide 2.5V to 5.5V Supply Range

Low Power Operation: 250μA per DAC at 3V

Individual Channel Power-Down to 1μA, Max

Ultralow Crosstalk Between DACs (<10μV)

High Rail-to-Rail Output Drive (±15mA, Min)

Double-Buffered Digital Inputs

Pin-Compatible 10-/8-Bit Versions (LTC1660/LTC1665)

Tiny 16-Lead Narrow SSOP

and 20-Lead 4mm × 5mm QFN Packages

1GND

OUTA

OUTB

OUTC

OUTD

REF

CS/LD

SCK

OUTH

OUTG

OUTF

OUTE

CLR

SDO

SDI

2600 BD

DAC A

3 14

4 13

(1)

(20)

(2)

(3)

(4)

(7)

(5)

(8)

(16)

(17)

(15)

(14)

(13)

(10)

(11)

(9)

DECODE

POWER-ON

RESET

CONTROL

LOGIC

32-BIT SHIFT REGISTER

DAC H

DAC B

DAC G

DAC C

DAC F

DAC D

DAC E

NOTE: NUMBERS IN PARENTHESIS REFER TO THE UFD PACKAGE

Differential Nonlinearity (LTC2600)

CODE

0 16384 32768 49152 65535

DNL (LSB)

2600 G21

1.0

0.8

0.6

0.4

0.2

–0.2

–0.4

–0.6

–0.8

–1.0

= 5V

REF

= 4.096V

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

Summary of content (20 pages)

PAGE 1
LTC2600/LTC2610/LTC2620 Octal 16-/14-/12-Bit Rail-to-Rail DACs in 16-Lead SSOP DESCRIPTION FEATURES n n n n n n n n n n Smallest Pin-Compatible Octal DACs: LTC2600: 16 Bits LTC2610: 14 Bits LTC2620: 12 Bits Guaranteed 16-Bit Monotonic Over Temperature Wide 2.5V to 5.
PAGE 2
LTC2600/LTC2610/LTC2620 ABSOLUTE MAXIMUM RATINGS (Note 1) Any Pin to GND ........................................... –0.3V to 6V Any Pin to VCC ............................................ –6V to 0.3V Operating Temperature Range LTC2600C/LTC2610C/LTC2620C ............. 0°C to 70°C LTC2600I/LTC2610I/LTC2620I............. –40°C to 85°C Storage Temperature Range.................. –65°C to 150°C Maximum Junction Temperature........................... 125°C Lead Temperature (Soldering, 10 sec) ...............
PAGE 3
LTC2600/LTC2610/LTC2620 ELECTRICAL CHARACTERISTICS The l denotes speciﬁcations which apply over the full operating temperature range, otherwise speciﬁcations are at TA = 25°C. VCC = 2.5V to 5.5V, VREF ≤ VCC, VOUT unloaded, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN LTC2620 TYP MAX MIN LTC2610 TYP MAX MIN LTC2600 TYP MAX UNITS DC Performance Resolution l 12 14 16 12 14 16 Monotonicity VCC = 5V, VREF = 4.096V (Note 2) l DNL Differential Nonlinearity VCC = 5V, VREF = 4.
PAGE 4
LTC2600/LTC2610/LTC2620 ELECTRICAL CHARACTERISTICS The l denotes speciﬁcations which apply over the full operating temperature range, otherwise speciﬁcations are at TA = 25°C. VCC = 2.5V to 5.5V, VREF ≤ VCC, VOUT unloaded, unless otherwise noted. SYMBOL PARAMETER LTC2600/LTC2610/LTC2620 MIN TYP MAX CONDITIONS UNITS Power Supply l VCC Positive Supply Voltage 2.
PAGE 5
LTC2600/LTC2610/LTC2620 TIMING CHARACTERISTICS The l denotes speciﬁcations which apply over the full operating temperature range, otherwise speciﬁcations are at TA = 25°C. (See Figure 1) (Note 6) SYMBOL PARAMETER LTC2600/LTC2610/LTC2620 MIN TYP MAX CONDITIONS UNITS VCC = 2.5V to 5.
PAGE 6
LTC2600/LTC2610/LTC2620 TYPICAL PERFORMANCE CHARACTERISTICS LTC2600 Integral Nonlinearity (INL) 32 Differential Nonlinearity (DNL) 1.0 VCC = 5V VREF = 4.096V 24 INL vs Temperature 32 VCC = 5V VREF = 4.096V 0.8 VCC = 5V VREF = 4.096V 24 0.6 16 0 –8 0.2 INL (LSB) DNL (LSB) 8 INL (LSB) 16 0.4 0 –0.2 INL (POS) 8 0 –8 INL (NEG) –0.4 –16 –0.6 –24 –32 –16 –24 –0.8 16384 0 32768 CODE 49152 –1.0 65535 0 16384 32768 CODE 49152 DNL vs Temperature VCC = 5V VREF = 4.096V 90 1.
PAGE 7
LTC2600/LTC2610/LTC2620 TYPICAL PERFORMANCE CHARACTERISTICS LTC2610 Differential Nonlinearity (DNL) Integral Nonlinearity (INL) 8 1.0 VCC = 5V VREF = 4.096V 6 VCC = 5V VREF = 4.096V 0.8 0.6 4 0.4 2 DNL (LSB) INL (LSB) Settling to ±1LSB 0 –2 VOUT 100μV/DIV 0.2 0 CS/LD 2V/DIV –0.2 –0.4 –4 8.9μs –0.6 –6 –0.8 –8 –1.0 0 4096 8192 CODE 12288 16383 2600 G30 2μs/DIV 0 4096 8192 CODE 12288 2600 G28 VCC = 5V, VREF = 4.
PAGE 8
LTC2600/LTC2610/LTC2620 TYPICAL PERFORMANCE CHARACTERISTICS LTC2600/LTC2610/LTC2620 Gain Error vs Temperature Zero-Scale Error vs Temperature 3 3 0.3 2.0 1.5 1.0 2 0.2 OFFSET ERROR (mV) GAIN ERROR (%FSR) 2.5 ZERO-SCALE ERROR (mV) Offset Error vs VCC 0.4 0.1 0 –0.1 0 –1 –0.2 0.5 –2 –0.3 0 –50 –30 –10 10 30 50 TEMPERATURE (°C) 70 90 –0.4 –50 –30 –10 10 30 50 TEMPERATURE (°C) 70 2600 G04 0.4 –3 2.5 90 3.5 3 4 VCC (V) 4.5 5 2600 G05 Gain Error vs VCC 5.
PAGE 9
LTC2600/LTC2610/LTC2620 TYPICAL PERFORMANCE CHARACTERISTICS LTC2600/LTC2610/LTC2620 VCC = 5V SWEEP SCK, SDI AND CS/LD 0V TO VCC 2.3 2.2 VCC = 5V VREF = 2V VOUT 0.5V/DIV 2.1 2.0 VOUT 1V/DIV DACs A TO G IN POWER-DOWN MODE 1.9 CS/LD 5V/DIV 1.8 CLR 5V/DIV 1.7 2.5μs/DIV 1.6 0.5 1 1.5 2 2.5 3 3.5 LOGIC VOLTAGE (V) 4 4.5 1μs/DIV 2600 G14 2600 G15 5 2600 G13 Output Voltage Noise, 0.
PAGE 10
LTC2600/LTC2610/LTC2620 PIN FUNCTIONS (GN/UFD) GND (Pin 1/Pin 20): Analog Ground. VOUTA to VOUTH (Pins 2-5 and 12-15/Pins 1-48 and 13-16): DAC Analog Voltage Outputs. The output range is 0 – VREF. REF (Pin 6/Pin 5): Reference Voltage Input. 0V ≤ VREF ≤ VCC. CS/LD (Pin 7/Pin 7): Serial Interface Chip Select/Load Input. When CS/LD is low, SCK is enabled for shifting data on SDI into the register. When CS/LD is taken high, SCK is disabled and the speciﬁed command (see Table 1) is executed.
PAGE 11
LTC2600/LTC2610/LTC2620 VOUTA 2 DAC A DAC REGISTER INPUT REGISTER INPUT REGISTER (2) VOUTB 3 DAC B DAC REGISTER INPUT REGISTER INPUT REGISTER (3) VOUTC 4 DAC C DAC REGISTER INPUT REGISTER INPUT REGISTER (4) VOUTD 5 DAC D INPUT REGISTER INPUT REGISTER (5) REF 6 (7) CS/LD 7 (8) SCK 8 (17) DAC REGISTER (1) 16 VCC DAC H 15 VOUTH (16) DAC REGISTER 1 DAC G 14 VOUTG (15) DAC REGISTER GND DAC F 13 VOUTF (14) DAC REGISTER (20) DAC REGISTER BLOCK DIAGRAM DAC E
PAGE 12
LTC2600/LTC2610/LTC2620 OPERATION Power-On Reset Serial Interface The LTC2600/LTC2610/LTC2620 clear the outputs to zero-scale when power is ﬁrst applied, making system initialization consistent and repeatable. The CS/LD input is level triggered. When this input is taken low, it acts as a chip-select signal, powering on the SDI and SCK buffers and enabling the input shift register. Data (SDI input) is transferred at the next 24 rising SCK edges.
PAGE 13
LTC2600/LTC2610/LTC2620 OPERATION INPUT WORD (LTC2600) COMMAND C3 C2 C1 C0 ADDRESS A3 A2 A1 DATA (16 BITS) A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB LSB 2600 TBL01 INPUT WORD (LTC2610) COMMAND C3 C2 C1 C0 ADDRESS A3 A2 A1 DATA (14 BITS + 2 DON’T-CARE BITS) A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB X X LSB 2600 TBL02 INPUT WORD (LTC2620) COMMAND C3 C2 C1 C0 ADDRESS A3 A2 A1 DATA (12 BITS + 4 DON’T-CARE BITS) A0 D11 D10 D9 D8 D7 D6 D5 MSB
PAGE 14
LTC2600/LTC2610/LTC2620 OPERATION Power-Down Mode Voltage Outputs For power-constrained applications, power-down mode can be used to reduce the supply current whenever less than eight outputs are needed. When in power-down, the buffer ampliﬁers and reference inputs are disabled, and draw essentially zero current. The DAC outputs are put into a high impedance state, and the output pins are passively pulled to ground through individual 90k resistors.
PAGE 15
LTC2600/LTC2610/LTC2620 OPERATION The GND pin functions both as the node to which the reference and output voltages are referred and as a return path for power currents in the device. Because of this, careful thought should be given to the grounding scheme and board layout in order to ensure rated performance. The PC board should have separate areas for the analog and digital sections of the circuit.
PAGE 16
X X SDI SDO SCK CS/LD 1 X X 2 X X 3 X 4 X X X DON’T CARE 5 C3 SDI C2 2 C1 3 X X 6 X X 7 C3 C2 10 C1 11 C2 C1 COMMAND WORD 9 C3 A1 7 ADDRESS WORD A2 6 A0 8 D15 9 D14 10 D12 12 D11 13 D10 14 24-BIT INPUT WORD D13 11 D9 15 D7 17 DATA WORD D8 16 D6 18 D5 C0 C0 A3 A3 A2 14 A1 15 A2 A1 ADDRESS WORD 13 A0 A0 16 17 D15 D15 PREVIOUS 32-BIT INPUT WORD 12 D14 D14 18 t2 t8 D9 D9 t4 23 PREVIOUS D15 t3 17 D10 D10 22 SDO t1 D
PAGE 17
LTC2600/LTC2610/LTC2620 OPERATION VREF = VCC VREF = VCC POSITIVE FSE OUTPUT VOLTAGE OUTPUT VOLTAGE INPUT CODE (c) OUTPUT VOLTAGE 0 0V NEGATIVE OFFSET 32, 768 INPUT CODE (a) 65, 535 INPUT CODE (b) 2600 F03 Figure 3. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative Offset for Codes Near Zero-Scale (c) Effect of Positive Full-Scale Error for Codes Near Full Scale PACKAGE DESCRIPTION GN Package 16-Lead Plastic SSOP (Narrow .
PAGE 18
LTC2600/LTC2610/LTC2620 PACKAGE DESCRIPTION UFD Package 20-Lead Plastic QFN (4mm × 5mm) (Reference LTC DWG # 05-08-1711 Rev B) 0.70 p 0.05 4.50 p 0.05 1.50 REF 3.10 p 0.05 2.65 p 0.05 3.65 p 0.05 PACKAGE OUTLINE 0.25 p 0.05 0.50 BSC 2.50 REF 4.10 p 0.05 5.50 p 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 p 0.10 (2 SIDES) 0.75 p 0.05 PIN 1 NOTCH R = 0.20 OR C = 0.35 1.50 REF R = 0.05 TYP 19 20 0.40 p 0.10 PIN 1 TOP MARK (NOTE 6) 1 2 5.
PAGE 19
LTC2600/LTC2610/LTC2620 REVISION HISTORY (Revision history begins at Rev D) REV DATE DESCRIPTION PAGE NUMBER D 03/10 Revise GN Part Markings in Order Information E 05/10 Changed “No Connect” pins to “Do Not Connect” in Pin Conﬁguration and Pin Functions sections 2 2, 10 2600fe Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use.
PAGE 20
LTC2600/LTC2610/LTC2620 TYPICAL APPLICATION Schematic for LTC2600 Demonstration Circuit DC579. The Outputs Are Measured by an Onboard LTC2428 1 4 3 2 1 VSS SDA A2 SCL A1 WP A0 VCC VREF VCC 1 TP1 TP2 5 R1, R3, R4 R1 are 4.99k, 1% 6 R3 R2 7.5k R4 11 7 C3 0.1μF 8 C2 0.1μF 6 REF CLR VCC VOUTA U1 24LC025 VOUTB 14 12 10 8 6 4 2 5V VCC C1 0.