Datasheet

ManualsBrandsLINEAR TECHNOLOGY ManualsData collecting ICsData acquisition IC - DA converter (DAC) MSOP 8

LTC2641/LTC2642

26412fc

For more information www.linear.com/LTC2641

Typical applicaTion

FeaTures

applicaTions

DescripTion

16-/14-/12-Bit V

OUT

DACs in

3mm × 3mm DFN

The LTC

2641/LTC2642 are families of 16-, 14- and 12-bit

unbuffered voltage output DACs. These DACs operate from

a single 2.7V to 5.5V supply and are guaranteed mono

tonic over temperature. The LTC2641A-16/LTC2642A-16

provide 16-bit performance (±1LSB INL and ±1LSB DNL)

over temperature. Unbuffered DAC outputs result in low

supply current of 120µA and a low offset error of ±1LSB.

Both the LTC2641 and LTC2642 feature a reference input

range of 2V to V

. V

OUT

swings from 0V to V

REF

. For

bipolar operation, the LTC2642 includes matched scaling

resistors for use with an external precision op amp (such

as the LT1678), generating a ±V

REF

output swing at R

The LTC2641/LTC2642 use a simple SPI/MICROWIRE

compatible 3-wire serial interface which can be operated

at clock rates up to 50MHz and can interface directly

with optocouplers for applications requiring isolation. A

power-on reset circuit clears the LTC2641’s DAC output

to zero scale and the LTC2642’s DAC output to midscale

when power is initially applied. A logic low on the CLR pin

asynchronously clears the DAC to zero scale (LTC2641)

or midscale (LTC2642). These DACs are all speciﬁed over

the commercial and industrial ranges.

Tiny 3mm × 3mm 8-Pin DFN Package

Maximum 16-Bit INL Error: ±1LSB over Temperature

Low 120µA Supply Current

Guaranteed Monotonic over Temperature

Low 0.5nV•sec Glitch Impulse

2.7V to 5.5V Single Supply Operation

Fast 1µs Settling Time to 16 Bits

Unbuffered Voltage Output Directly Drives 60k Loads

50MHz SPI/QSPI/MICROWIRE

Compatible

Serial Interface

Power-On Reset Clears DAC Output to Zero Scale

(LTC2641) or Midscale (LTC2642)

Schmitt-Trigger Inputs for Direct Optocoupler

Interface

Asynchronous CLR Pin

8-Lead MSOP and 3mm × 3mm DFN Packages

(LTC2641)

10-Lead MSOP and 3mm × 3mm DFN Packages

(LTC2642)

High Resolution Offset and Gain Adjustment

Process Control and Industrial Automation

Automatic Test Equipment

Data Aquisition Systems

Bipolar 16-Bit DAC

LTC2642-16 Integral Nonlinearity

–

16-BIT DATA LATCH

CONTROL

LOGIC

16-BIT DAC

1/2 LT1678

INV

REF

2V TO

BIPOLAR V

OUT

–V

REF

TO V

REF

0.1µF

5pF

REF

2.7V TO 5.5V

OUT

GND

26412 TA01a

16-BIT SHIFT REGISTER

1µF0.1µF

LTC2642

POWER-ON

RESET

SCLK

DIN

CLR

CODE

–1.0

INL (LSB)

–0.8

–0.4

–0.2

1.0

0.4

16384

32768

26412 TA01b

–0.6

0.6

0.8

0.2

49152

65535

= 5V

REF

= 2.5V

±2.5V RANGE

INL 25°C

INL 90°C

INL –45°C

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the

property of their respective owners.

Summary of content (24 pages)

PAGE 1
LTC2641/LTC2642 16-/14-/12-Bit VOUT DACs in 3mm × 3mm DFN Features n n n n n n n n n n n n n n Description Tiny 3mm × 3mm 8-Pin DFN Package Maximum 16-Bit INL Error: ±1LSB over Temperature Low 120µA Supply Current Guaranteed Monotonic over Temperature Low 0.5nV•sec Glitch Impulse 2.7V to 5.
PAGE 2
LTC2641/LTC2642 Absolute Maximum Ratings (Note 1) VDD to GND................................................... –0.3V to 6V CS, SCLK, DIN, CLR to GND......................... –0.3V to (VDD + 0.3V) or 6V REF, VOUT, INV to GND......... –0.3V to (VDD + 0.3V) or 6V RFB to INV........................................................ –6V to 6V RFB to GND...................................................... –6V to 6V GND to GND (S8 Package) OBSOLETE ..... –0.3V to 0.
PAGE 3
LTC2641/LTC2642 Order Information LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2641ACDD-16#PBF LTC2641ACDD-16#TRPBF LCZP 8-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C LTC2641CDD-16#PBF LTC2641CDD-16#TRPBF LCZP 8-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C LTC2641CDD-14#PBF LTC2641CDD-14#TRPBF LCZN 8-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C LTC2641CDD-12#PBF LTC2641CDD-12#TRPBF LCZM 8-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C LTC2641AIDD-16#PBF LTC2
PAGE 4
LTC2641/LTC2642 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 3V or 5V, VREF = 2.5V, CL = 10pF, GND = 0, RL = ∞ unless otherwise specified.
PAGE 5
LTC2641/LTC2642 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 3V or 5V, VREF = 2.5V, CL = 10pF, GND = 0, RL = ∞ unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN IIN Digital Input Current VIN = GND to VDD l CIN Digital Input Capacitance (Note 6) l VH Hysteresis Voltage TYP 3 MAX UNITS ±1 µA 10 pF 0.
PAGE 6
LTC2641/LTC2642 Typical Performance Characteristics Integral Nonlinearity (INL) vs Supply (VDD) Integral Nonlinearity (INL) LTC2642-16 VREF = 2.5V VDD = 5V 0.8 0.6 INL vs VREF 1.0 VREF = 2.5V 0.8 0.4 0.2 0.2 0 –0.2 0.6 +INL 0 –INL –0.2 –0.6 –0.6 –0.6 –0.8 –0.8 –0.8 –1.0 –1.0 –1.0 32768 CODE 65535 49152 3 2 4 VDD (V) 6 5 1.0 1.0 VREF = 2.5V 0.8 0.6 0.4 0.4 0.2 0.2 DNL (LSB) DNL (LSB) –0.2 +DNL 0 –DNL –0.2 0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –0.8 –1.0 –1.
PAGE 7
LTC2641/LTC2642 Typical Performance Characteristics Unbuffered Zero Scale Error vs Temperature (LTC2641-16) Bipolar Gain Error vs Temperature 5 VREF = 2.5V VDD = 5V 1.0 0.8 0.6 0.6 2 0.4 0.4 1 0.2 0.2 0 –1 FSE (LSB) 0.8 ZSE (LSB) BGE (LSB) 1.0 3 4 0 –0.2 –0.4 –0.4 –3 –0.6 –0.6 –4 –0.8 –0.8 –5 –40 –1.0 –40 –15 35 10 TEMPERATURE (°C) 60 85 –15 35 10 TEMPERATURE (°C) 60 14-Bit Differential Nonlinearity (DNL) (LTC2642-14) 1.0 LTC2642-14 VREF = 2.5V VDD = 5V 0.8 0.6 0.6 0.
PAGE 8
LTC2641/LTC2642 Typical Performance Characteristics Supply Current (IDD) vs Temperature 150 VREF = 2.5V 125 800 700 75 50 75 –15 10 35 TEMPERATURE (°C) 0 85 60 2.5 3.5 3 4 4.5 5 150 100 IDD (µA) 100 IDD (µA) 125 75 50 25 25 2.5 3 3.5 4 4.5 5 0 VREF (V) 1.5 2 VREF (V) 2.5 3 26412 G25 CODE 32768 500ns/DIV CODE 32767 26412 G24 VOUT vs VDD = 0V to 5.5V (POR Function) LTC2641 VDD = VREF 0V TO 5.
PAGE 9
LTC2641/LTC2642 Pin Functions LTC2641 – MSOP, DFN Packages REF (Pin 1): Reference Voltage Input. Apply an external reference at REF between 2V and VDD. CS (Pin 2): Serial Interface Chip Select/Load Input. When CS is low, SCLK is enabled for shifting in data on DIN. When CS is taken high, SCLK is disabled, the 16-bit input word is latched and the DAC is updated. SCLK (Pin 3): Serial Interface Clock Input. CMOS and TTL compatible. DIN (Pin 4): Serial Interface Data Input.
PAGE 10
LTC2641/LTC2642 Block Diagrams LTC2641 - SO OBSOLETE PACKAGE LTC2641 - MSOP, DFN 7 VDD 1 8 REF LTC2641-16 LTC2641-14 LTC2641-12 POWER-ON RESET 2 3 4 5 DIN 16-/14-/12-BIT DAC VOUT 6 CLR 4 CONTROL LOGIC REF LTC2641-16 CS SCLK 3 VDD 5 16-BIT DATA LATCH 6 16-BIT SHIFT REGISTER GND 7 8 POWER-ON RESET 16-/14-/12-BIT DAC CONTROL LOGIC 16-BIT DATA LATCH VOUT 1 CS SCLK DIN GND 16-BIT SHIFT REGISTER 2641 BD01a GND 2 2641 BD01b LTC2642 9 VDD 1 REF RFB LTC2642-16 LTC2642-14 LTC2642-1
PAGE 11
LTC2641/LTC2642 Timing Diagram t1 t2 t3 1 SCK 2 t4 t6 3 15 16 t8 SDI t5 t7 26412 TD CS/LD Operation General Description The LTC2641/LTC2642 family of 16-/14-/12-bit voltage output DACs offer full 16-bit performance with less than ±1LSB integral linearity error and less than ±1LSB differential linearity error, guaranteeing monotonic operation. They operate from a single supply ranging from 2.7V to 5.5V, consuming 120µA (typical).
PAGE 12
LTC2641/LTC2642 OPERATION high-to-low transition, the data on DIN is loaded, MSB first, into the shift register on each rising edge of the serial clock input (SCLK). After 16 data bits have been loaded into the serial input register, a low-to-high transition on CS transfers the data to the 16-bit DAC latch, updating the DAC output (see Figures 1a, 1b, 1c). While CS remains high, the serial input shift register is disabled.
PAGE 13
LTC2641/LTC2642 Applications Information Unipolar Configuration The external amplifier provides a unity-gain buffer. The LTC2642 can also be used in unipolar configuration by tying RFB and INV to REF . This provides power-up and clear to midscale. Figure 2 shows a typical unipolar DAC application for the LTC2641. Tables 1a, 1b and 1c show the unipolar binary code tables for 16-bit, 14-bit and 12-bit operation. VREF 2.5V 0.1µF 5V/3V 4.7µF OUT IN 5V Table 1a.
PAGE 14
LTC2641/LTC2642 Applications Information Bipolar Configuration The amplifier circuit provides a gain of +2 from the VOUT pin, and gain of –1 from VREF . Tables 2a, 2b and 2c show the bipolar offset binary code tables for 16-bit, 14-bit and 12-bit operation. Figure 3 shows a typical bipolar DAC application for the LTC2642. The on-chip bipolar offset/gain resistors, RFB and RINV, are connected to an external amplifier to produce a bipolar output swing from –VREF to VREF at the RFB pin. VREF 2.5V 5V/3V 0.
PAGE 15
LTC2641/LTC2642 Applications Information Unbuffered Operation and VOUT Loading The DAC output is available directly at the VOUT pin, which swings from GND to VREF . Unbuffered operation provides the lowest possible offset, full-scale and linearity errors, the fastest settling time and minimum power consumption. However, unbuffered operation requires that appropriate loading be maintained on the VOUT pin.
PAGE 16
LTC2641/LTC2642 Applications Information such as the LTC6078 is suitable, if the application does not require linear operation very near to GND, or zero scale (Figure 2). The LTC6078 typically swings to within 1mV of GND if it is not required to sink any load current. For an LSB size of 38µV, 1mV represents 26 missing codes near zero scale. Linearity will be degraded over a somewhat larger range of codes above GND.
PAGE 17
LTC2641/LTC2642 Applications Information Op Amp Specifications and Bipolar DAC Accuracy The op amp contributions to unipolar DAC error discussed above apply equally to bipolar operation. The bipolar application circuit gains up the DAC span, and all errors, by a factor of 2. Since the LSB size also doubles, the errors in LSBs are identical in unipolar and bipolar modes. One added error in bipolar mode comes from IB (IN–), which flows through RFB to generate an offset.
PAGE 18
LTC2641/LTC2642 Applications Information as the external reference remains stable with the added capacative loading. Digital Inputs and Interface Logic All of the digital inputs include Schmitt-trigger buffers to accept slow transition interfaces. This means that optocuplers can interface directly to the LTC2641/LTC2642 without additional external logic. Digital input hysteresis is typically 150mV. The digital inputs are compatible with TTL/CMOS-logic levels.
PAGE 19
LTC2641/LTC2642 Applications Information on the digital inputs is imperceptible, thanks to the digital input hysteresis) Just by maintaining separate areas on the GND plane where analog and digital return currents naturally flow, good results are generally achieved. Only after this has been done, it is sometimes useful to interrupt the ground plane with strategically placed “slots”, to prevent the digital ground currents from fringing into the analog portion of the plane.
PAGE 20
LTC2641/LTC2642 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. DD Package 10-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1699 Rev C) 0.70 ±0.05 3.55 ±0.05 1.65 ±0.05 2.15 ±0.05 (2 SIDES) PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 2.38 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 3.00 ±0.10 (4 SIDES) R = 0.125 TYP 6 0.40 ± 0.10 10 1.65 ± 0.10 (2 SIDES) PIN 1 NOTCH R = 0.20 OR 0.
PAGE 21
LTC2641/LTC2642 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. S8 Package 8-Lead Plastic Small Outline (Narrow .150 Inch) (Reference LTC DWG # 05-08-1610 Rev G) .189 – .197 (4.801 – 5.004) NOTE 3 .045 ±.005 .050 BSC 8 .245 MIN .160 ±.005 .010 – .020 × 45° (0.254 – 0.508) 2 .053 – .069 (1.346 – 1.752) 0°– 8° TYP .016 – .050 (0.406 – 1.270) 5 .150 – .157 (3.810 – 3.988) NOTE 3 1 RECOMMENDED SOLDER PAD LAYOUT .008 – .
PAGE 22
LTC2641/LTC2642 Package Description MS8 Package 8-Lead Plastic MSOP (Reference LTC DWG # 05-08-1660 Rev G) 3.00 ±0.102 (.118 ±.004) (NOTE 3) 0.889 ±0.127 (.035 ±.005) 0.254 (.010) 8 7 6 5 3.00 ±0.102 (.118 ±.004) (NOTE 4) 4.90 ±0.152 (.193 ±.006) DETAIL “A” 0.52 (.0205) REF 0° – 6° TYP GAUGE PLANE 5.10 (.201) MIN 3.20 – 3.45 (.126 – .136) 0.53 ±0.152 (.021 ±.006) DETAIL “A” 0.42 ± 0.038 (.0165 ±.0015) TYP 0.65 (.0256) BSC 1 2 3 4 1.10 (.043) MAX 0.86 (.034) REF 0.18 (.
PAGE 23
LTC2641/LTC2642 Revision History (Revision history begins at Rev C) REV DATE DESCRIPTION PAGE NUMBER C 12/13 Marked S8 package as Obsolete 2, 3, 9, 10, 18, 21 26412fc Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. For more information www.
PAGE 24
LTC2641/LTC2642 Typical Application Wide Range Current Load Sinks 0A to 2.5A 5V 0.1µF VREF 2.5V 0.1µF 4.7µF OUT 5V GND 1 7 IN LT1019CS8-2.5 REF VDD 10V LTC2641-16 2 16-BIT DAC CS 3 SCLK 4 DIN 5 CLR VOUT 6 0.1µF ISINK 0A TO 2.5A + 1k LTC2054HV – IRLZ44 0.