Datasheet

LTC2641/LTC2642
11
26412fc
For more information www.linear.com/LTC2641
operaTion
TiMing DiagraM
General Description
The LTC2641/LTC2642 family of 16-/14-/12-bit voltage
output DACs offer full 16-bit performance with less than
±1LSB integral linearity error and less than ±1LSB differ
-
ential linearity error, guaranteeing monotonic operation.
Th
ey operate from a single supply ranging from 2.7V to
5.5V, consuming 120µA (typical). An external voltage
reference of 2V to V
DD
determines the DAC’s full-scale
output voltage. A 3-wire serial interface allows the
LTC2641/LTC2642 to fit into a small 8-/10-pin MSOP or
DFN 3mm × 3mm package.
Digital-to-Analog Architecture
The DAC architecture is a voltage switching mode resis
-
tor ladder using precision thin-film resistors and CMOS
switches. The LTC2641/LTC2642 DAC resistor ladders are
composed of a proprietary arrangement of matched DAC
sections. The four MSBs are decoded to drive 15 equally
weighted segments, and the remaining lower bits drive
successively lower weighted sections. Major carry glitch
impulse is very low at 500pV•sec, C
L
= 10pF, ten times
lower than previous DACs of this type.
The digital-to-analog transfer function at the V
OUT
pin
is:
V
OUT(IDEAL)
=
k
2
N






V
REF
where k is the decimal equivalent of the binary DAC input
code, N is the resolution, and V
REF
is between 2.0V and
V
DD
(see Tables 1a, 1b and 1c).
The LTC2642 includes matched resistors that are tied
to an external amplifier to provide bipolar output swing
(Figure 2). The bipolar transfer function at the RFB pin is:
V
OUT _BIPOLAR(IDEAL)
= V
REF
k
2
N–1
– 1






(see Tables 2a, 2b and 2c).
Serial Interface
The LTC2641/LTC2642 communicates via a standard
3-wire SPI/QSPI/MICROWIRE compatible interface. The
chip select input (CS) controls and frames the loading
of serial data from the data input (DIN). Following a CS
t
1
SCK
SDI
CS/LD
t
5
t
7
t
2
t
6
t
8
26412 TD
1 2 3 15 16
t
3
t
4